hrccgrhrcuhac.r

This commit is contained in:
Nikolaj
2021-12-22 13:49:32 +01:00
parent bdfb4ec7c2
commit e834df4ddd
2 changed files with 5 additions and 6 deletions

View File

@ -122,17 +122,16 @@ int main(int argc, char* argv[]) {
bool is_leaq7 = is(LEAQ7, major_op);
bool is_imm_cbranch = is(IMM_CBRANCH, major_op);
// Right now, we can only execute instructions with a size of 2.
// from info above determine the instruction size
// Determining instruction size
bool size_is_2 = (is_return_or_stop || is_reg_arithmetic || is_reg_movq || is_reg_movq_mem || is_leaq2);
val size_2 = use_if(size_is_2, from_int(2));
bool size_is_3 = (is_leaq3);
val size_3 = use_if(size_is_3, from_int(3));
bool size_is_6 = (is_cflow || is_imm_arithmetic || is_imm_movq || is_imm_movq_mem || is_leaq6);
val size_6 = use_if(size_is_6, from_int(6));
bool size_is_7 = (is_leaq7);
val size_7 = use_if(size_is_7, from_int(7));
bool size_is_10 = (is_imm_cbranch);
val size_2 = use_if(size_is_2, from_int(2));
val size_3 = use_if(size_is_3, from_int(3));
val size_6 = use_if(size_is_6, from_int(6));
val size_7 = use_if(size_is_7, from_int(7));
val size_10 = use_if(size_is_10, from_int(10));
val add_1 = add(size_2, size_3);

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A5/sim

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