diff --git a/Fasto/CodeGen.fs b/Fasto/CodeGen.fs
index ac8efbd..64bd779 100644
--- a/Fasto/CodeGen.fs
+++ b/Fasto/CodeGen.fs
@@ -156,7 +156,7 @@ let dynalloc (size_reg : Mips.reg,
         ; Mips.ADD (HP, HP, tmp_reg)
         ; Mips.SW (size_reg, place, 0) ]
 
-    code1 @ code2 @ code3
+    [Mips.COMMENT "dynalloc"] @ code1 @ code2 @ code3
 
 (* Pushing arguments on the stack: *)
 (* For each register 'r' in 'rs', copy them to registers from
@@ -540,7 +540,8 @@ let rec compileExp  (e      : TypedExp)
               ; Mips.J loop_beg
               ; Mips.LABEL loop_end
               ]
-      arr_code
+      [Mips.COMMENT "map"]
+       @ arr_code
        @ get_size
        @ dynalloc (size_reg, place, ret_type)
        @ init_regs
diff --git a/Fasto/CopyConstPropFold.fs b/Fasto/CopyConstPropFold.fs
index c8c1b1b..9d2ef24 100644
--- a/Fasto/CopyConstPropFold.fs
+++ b/Fasto/CopyConstPropFold.fs
@@ -33,21 +33,21 @@ let rec copyConstPropFoldExp (vtable : VarTable)
                 | Some (ConstProp x) -> Constant (x, pos)
                 | Some (VarProp x)   -> Var (x, pos)
                 | _                  -> Var (name, pos)
-        | Index (name, e, t, pos) ->
+        | Index (name, e2, t, pos) ->
             (* TODO project task 3:
                 Should probably do the same as the `Var` case, for
                 the array name, and optimize the index expression `e` as well.
             *)
             let name' = SymTab.lookup name vtable
-            let e'    = copyConstPropFoldExp vtable e
+            let e2'    = copyConstPropFoldExp vtable e2
             match name' with
-                | Some (VarProp x)   -> Index (x, e', t, pos)
-                | _                  -> Index (name, e', t, pos)
+                | Some (VarProp x)   -> Index (x, e2', t, pos)
+                | _                  -> Index (name, e2', t, pos)
 
         | Let (Dec (name, e, decpos), body, pos) ->
             let e' = copyConstPropFoldExp vtable e
             match e' with
-                | Var (name', pos') ->
+                | Var (name', _) ->
                     (* TODO project task 3:
                         Hint: I have discovered a variable-copy statement `let x = a`.
                               I should probably record it in the `vtable` by
@@ -57,7 +57,7 @@ let rec copyConstPropFoldExp (vtable : VarTable)
                     let vtable' = SymTab.bind name (VarProp name') vtable
                     let body' = copyConstPropFoldExp vtable' body
                     Let (Dec (name, e', decpos), body', pos)
-                | Constant (constval, pos') ->
+                | Constant (constval, _) ->
                     (* TODO project task 3:
                         Hint: I have discovered a constant-copy statement `let x = 5`.
                               I should probably record it in the `vtable` by
@@ -67,7 +67,7 @@ let rec copyConstPropFoldExp (vtable : VarTable)
                     let vtable' = SymTab.bind name (ConstProp constval) vtable
                     let body' = copyConstPropFoldExp vtable' body
                     Let (Dec (name, e', decpos), body', pos)
-                | Let (Dec (name', e'', decpos'), body', pos') ->
+                | Let (Dec (name2, e2, decpos2), body2, pos2) ->
                     (* TODO project task 3:
                         Hint: this has the structure
                                 `let y = (let x = e1 in e2) in e3`
@@ -79,8 +79,10 @@ let rec copyConstPropFoldExp (vtable : VarTable)
                         restructured, semantically-equivalent expression:
                                 `let x = e1 in let y = e2 in e3`
                     *)
-                    let let' = Let (Dec (name, body', decpos), body, pos)
-                    copyConstPropFoldExp vtable (Let (Dec (name', e'', decpos'), let', pos'))
+                    let e2' = copyConstPropFoldExp vtable e2
+                    let body2' = copyConstPropFoldExp vtable body2
+                    let body' = copyConstPropFoldExp vtable body
+                    Let (Dec (name, Let (Dec (name2, e2', decpos2), body2', pos2), decpos), body', pos)
                 | _ -> (* Fallthrough - for everything else, do nothing *)
                     let body' = copyConstPropFoldExp vtable body
                     Let (Dec (name, e', decpos), body', pos)
@@ -92,11 +94,33 @@ let rec copyConstPropFoldExp (vtable : VarTable)
                      1 * x = ?
                      x * 0 = ?
             *)
-            Times (e1, e2, pos)
+            let e1' = copyConstPropFoldExp vtable e1
+            let e2' = copyConstPropFoldExp vtable e2
+            match (e1', e2') with
+                | (Constant (IntVal x, _), Constant (IntVal y, _)) ->
+                    Constant (IntVal (x * y), pos)
+                | (Constant (IntVal 0, _), _) ->
+                    Constant (IntVal 0, pos)
+                | (_, Constant (IntVal 0, _)) ->
+                    Constant (IntVal 0, pos)
+                | (Constant (IntVal 1, _), _) ->
+                    e2'
+                | (_, Constant (IntVal 1, _)) ->
+                    e1'
+                | _ -> Times (e1, e2, pos)
         | And (e1, e2, pos) ->
             (* TODO project task 3: see above. You may inspire yourself from
                `Or` below, but that only scratches the surface of what's possible *)
-            And (e1, e2, pos)
+            let e1' = copyConstPropFoldExp vtable e1
+            let e2' = copyConstPropFoldExp vtable e2
+            match (e1', e2') with
+                | (Constant (BoolVal a, _), Constant (BoolVal b, _)) ->
+                    Constant (BoolVal (a && b), pos)
+                | (Constant (BoolVal false, _), _) ->
+                    Constant (BoolVal false, pos)
+                | (_, Constant (BoolVal false, _)) ->
+                    Constant (BoolVal false, pos)
+                | _ -> And (e1', e2', pos)
         | Constant (x,pos) -> Constant (x,pos)
         | StringLit (x,pos) -> StringLit (x,pos)
         | ArrayLit (es, t, pos) ->
diff --git a/Fasto/Fasto.fsx b/Fasto/Fasto.fsx
index 32a0840..789f4f8 100644
--- a/Fasto/Fasto.fsx
+++ b/Fasto/Fasto.fsx
@@ -149,7 +149,9 @@ let parseFastoFile (filename : string) : AbSyn.UntypedProg =
 let compile (filename : string) optimiser : Unit =
     let pgm = parseFastoFile filename
     let pgm_decorated  = TypeChecker.checkProg pgm
+    //printfn "%A" pgm_decorated
     let pgm_optimised  = optimiser pgm_decorated
+    //printfn "%A" pgm_optimised
     let mips_code      = CodeGen.compile pgm_optimised
     let mips_code_text = Mips.ppMipsProg mips_code
     saveFile (filename + ".asm") mips_code_text
diff --git a/tests/copyConstPropFold0.asm b/tests/copyConstPropFold0.asm
index 824fcda..fa6f634 100644
--- a/tests/copyConstPropFold0.asm
+++ b/tests/copyConstPropFold0.asm
@@ -48,24 +48,13 @@ main:
 	jal	getint
 # was:	jal	getint, $2
 # 	ori	_letBind_11_,$2,0
-	ori	$4, $2, 0
-# was:	ori	_letBind_13_, _letBind_11_, 0
-	ori	$2, $0, 2
+# 	ori	_letBind_13_,_letBind_11_,0
+	ori	$0, $0, 2
 # was:	ori	_letBind_14_, $0, 2
-# 	ori	_plus_L_17_,_letBind_13_,0
-	ori	$3, $0, 2
-# was:	ori	_plus_R_18_, $0, 2
-	add	$3, $4, $3
-# was:	add	_times_L_15_, _plus_L_17_, _plus_R_18_
-# 	ori	_minus_L_19_,_letBind_14_,0
-	ori	$4, $0, 2
-# was:	ori	_minus_R_20_, $0, 2
-	sub	$2, $2, $4
-# was:	sub	_times_R_16_, _minus_L_19_, _minus_R_20_
-	mul	$16, $3, $2
-# was:	mul	_letBind_12_, _times_L_15_, _times_R_16_
-# 	ori	_tmp_21_,_letBind_12_,0
-# 	ori	_mainres_10_,_tmp_21_,0
+	ori	$16, $0, 0
+# was:	ori	_letBind_12_, $0, 0
+# 	ori	_tmp_15_,_letBind_12_,0
+# 	ori	_mainres_10_,_tmp_15_,0
 	ori	$2, $16, 0
 # was:	ori	$2, _mainres_10_, 0
 	jal	putint
diff --git a/tests/copyConstPropFold1.asm b/tests/copyConstPropFold1.asm
index 3db0396..28f9cda 100644
--- a/tests/copyConstPropFold1.asm
+++ b/tests/copyConstPropFold1.asm
@@ -34,6 +34,7 @@ main:
 # was:	la	$6, _Msg_IllegalArraySize_
 	j	_RuntimeError_
 _safe_lab_5_:
+# dynalloc
 	ori	$2, $28, 0
 # was:	ori	_letBind_3_, $28, 0
 	sll	$4, $3, 2
@@ -44,20 +45,20 @@ _safe_lab_5_:
 # was:	add	$28, $28, _tmp_11_
 	sw	$3, 0($2)
 # was:	sw	_size_reg_4_, 0(_letBind_3_)
-	addi	$5, $2, 4
+	addi	$6, $2, 4
 # was:	addi	_addr_reg_6_, _letBind_3_, 4
-	ori	$4, $0, 0
+	ori	$5, $0, 0
 # was:	ori	_i_reg_7_, $0, 0
 _loop_beg_8_:
-	sub	$6, $4, $3
+	sub	$4, $5, $3
 # was:	sub	_tmp_reg_10_, _i_reg_7_, _size_reg_4_
-	bgez	$6, _loop_end_9_
+	bgez	$4, _loop_end_9_
 # was:	bgez	_tmp_reg_10_, _loop_end_9_
-	sw	$4, 0($5)
+	sw	$5, 0($6)
 # was:	sw	_i_reg_7_, 0(_addr_reg_6_)
-	addi	$5, $5, 4
+	addi	$6, $6, 4
 # was:	addi	_addr_reg_6_, _addr_reg_6_, 4
-	addi	$4, $4, 1
+	addi	$5, $5, 1
 # was:	addi	_i_reg_7_, _i_reg_7_, 1
 	j	_loop_beg_8_
 _loop_end_9_:
@@ -86,13 +87,9 @@ _safe_lab_19_:
 # was:	sll	_arr_ind_14_, _arr_ind_14_, 2
 	add	$3, $3, $4
 # was:	add	_arr_reg_15_, _arr_reg_15_, _arr_ind_14_
-	lw	$2, 0($3)
+	lw	$16, 0($3)
 # was:	lw	_letBind_13_, 0(_arr_reg_15_)
-# 	ori	_times_L_21_,_letBind_13_,0
-	ori	$3, $0, 1
-# was:	ori	_times_R_22_, $0, 1
-	mul	$16, $2, $3
-# was:	mul	_tmp_20_, _times_L_21_, _times_R_22_
+# 	ori	_tmp_20_,_letBind_13_,0
 # 	ori	_mainres_1_,_tmp_20_,0
 	ori	$2, $16, 0
 # was:	ori	$2, _mainres_1_, 0
diff --git a/tests/filter-on-2darr.asm b/tests/filter-on-2darr.asm
index 04c3955..cf49951 100644
--- a/tests/filter-on-2darr.asm
+++ b/tests/filter-on-2darr.asm
@@ -46,9 +46,11 @@ write_1darr:
 	sw	$16, -8($29)
 	addi	$29, $29, -28
 # 	ori	_param_x_4_,$2,0
+# map
 # 	ori	_arr_reg_7_,_param_x_4_,0
 	lw	$16, 0($2)
 # was:	lw	_size_reg_6_, 0(_arr_reg_7_)
+# dynalloc
 	ori	$17, $28, 0
 # was:	ori	_write_1darrres_5_, $28, 0
 	sll	$3, $16, 2
@@ -107,9 +109,11 @@ write_2darr:
 	sw	$16, -8($29)
 	addi	$29, $29, -28
 # 	ori	_param_x_17_,$2,0
+# map
 # 	ori	_arr_reg_20_,_param_x_17_,0
 	lw	$16, 0($2)
 # was:	lw	_size_reg_19_, 0(_arr_reg_20_)
+# dynalloc
 	ori	$17, $28, 0
 # was:	ori	_write_2darrres_18_, $28, 0
 	sll	$3, $16, 2
@@ -199,6 +203,7 @@ main:
 	jal	getint
 # was:	jal	getint, $2
 # 	ori	_letBind_40_,$2,0
+# map
 	ori	$3, $2, 0
 # was:	ori	_size_reg_46_, _letBind_40_, 0
 	bgez	$3, _safe_lab_47_
@@ -209,6 +214,7 @@ main:
 # was:	la	$6, _Msg_IllegalArraySize_
 	j	_RuntimeError_
 _safe_lab_47_:
+# dynalloc
 	ori	$2, $28, 0
 # was:	ori	_arr_reg_43_, $28, 0
 	sll	$4, $3, 2
@@ -238,6 +244,7 @@ _loop_beg_50_:
 _loop_end_51_:
 	lw	$3, 0($2)
 # was:	lw	_size_reg_42_, 0(_arr_reg_43_)
+# dynalloc
 	ori	$4, $28, 0
 # was:	ori	_letBind_41_, $28, 0
 	sll	$5, $3, 2
@@ -277,6 +284,7 @@ _loop_beg_56_:
 # was:	la	$6, _Msg_IllegalArraySize_
 	j	_RuntimeError_
 _safe_lab_63_:
+# dynalloc
 	ori	$2, $28, 0
 # was:	ori	_fun_arg_res_59_, $28, 0
 	sll	$9, $8, 2
@@ -316,6 +324,7 @@ _loop_end_57_:
 # 	ori	_arr_reg_73_,_letBind_41_,0
 	lw	$17, 0($4)
 # was:	lw	_size_reg_72_, 0(_arr_reg_73_)
+# dynalloc
 	ori	$16, $28, 0
 # was:	ori	_letBind_71_, $28, 0
 	sll	$2, $17, 2
diff --git a/tests/filter.asm b/tests/filter.asm
index 670ee85..cd1420c 100644
--- a/tests/filter.asm
+++ b/tests/filter.asm
@@ -2,41 +2,27 @@
 	.globl	main
 	la	$28, _heap_
 	la	$4, _true
-# was:	la	_true_addr, _true
 	ori	$3, $0, 4
-# was:	ori	_true_init, $0, 4
 	sw	$3, 0($4)
-# was:	sw	_true_init, 0(_true_addr)
 	la	$3, _false
-# was:	la	_false_addr, _false
 	ori	$4, $0, 5
-# was:	ori	_false_init, $0, 5
 	sw	$4, 0($3)
-# was:	sw	_false_init, 0(_false_addr)
 	jal	main
 _stop_:
 	ori	$2, $0, 10
 	syscall
-# Function write_int
 write_int:
 	sw	$31, -4($29)
 	sw	$16, -8($29)
 	addi	$29, $29, -12
-# 	ori	_param_x_1_,$2,0
 	ori	$16, $2, 0
-# was:	ori	_tmp_3_, _param_x_1_, 0
-# 	ori	_write_intres_2_,_tmp_3_,0
 	ori	$2, $16, 0
-# was:	ori	$2, _write_intres_2_, 0
 	jal	putint
-# was:	jal	putint, $2
 	ori	$2, $16, 0
-# was:	ori	$2, _write_intres_2_, 0
 	addi	$29, $29, 12
 	lw	$16, -8($29)
 	lw	$31, -4($29)
 	jr	$31
-# Function write_int_arr
 write_int_arr:
 	sw	$31, -4($29)
 	sw	$20, -24($29)
@@ -45,50 +31,27 @@ write_int_arr:
 	sw	$17, -12($29)
 	sw	$16, -8($29)
 	addi	$29, $29, -28
-# 	ori	_param_x_4_,$2,0
-# 	ori	_arr_reg_7_,_param_x_4_,0
 	lw	$16, 0($2)
-# was:	lw	_size_reg_6_, 0(_arr_reg_7_)
 	ori	$17, $28, 0
-# was:	ori	_write_int_arrres_5_, $28, 0
 	sll	$3, $16, 2
-# was:	sll	_tmp_16_, _size_reg_6_, 2
 	addi	$3, $3, 4
-# was:	addi	_tmp_16_, _tmp_16_, 4
 	add	$28, $28, $3
-# was:	add	$28, $28, _tmp_16_
 	sw	$16, 0($17)
-# was:	sw	_size_reg_6_, 0(_write_int_arrres_5_)
 	addi	$18, $17, 4
-# was:	addi	_addr_reg_10_, _write_int_arrres_5_, 4
 	ori	$19, $0, 0
-# was:	ori	_i_reg_11_, $0, 0
 	addi	$20, $2, 4
-# was:	addi	_elem_reg_8_, _arr_reg_7_, 4
 _loop_beg_12_:
 	sub	$2, $19, $16
-# was:	sub	_tmp_reg_14_, _i_reg_11_, _size_reg_6_
 	bgez	$2, _loop_end_13_
-# was:	bgez	_tmp_reg_14_, _loop_end_13_
 	lw	$2, 0($20)
-# was:	lw	_res_reg_9_, 0(_elem_reg_8_)
 	addi	$20, $20, 4
-# was:	addi	_elem_reg_8_, _elem_reg_8_, 4
-# 	ori	$2,_res_reg_9_,0
 	jal	write_int
-# was:	jal	write_int, $2
-# 	ori	_tmp_reg_15_,$2,0
-# 	ori	_res_reg_9_,_tmp_reg_15_,0
 	sw	$2, 0($18)
-# was:	sw	_res_reg_9_, 0(_addr_reg_10_)
 	addi	$18, $18, 4
-# was:	addi	_addr_reg_10_, _addr_reg_10_, 4
 	addi	$19, $19, 1
-# was:	addi	_i_reg_11_, _i_reg_11_, 1
 	j	_loop_beg_12_
 _loop_end_13_:
 	ori	$2, $17, 0
-# was:	ori	$2, _write_int_arrres_5_, 0
 	addi	$29, $29, 28
 	lw	$20, -24($29)
 	lw	$19, -20($29)
@@ -97,34 +60,21 @@ _loop_end_13_:
 	lw	$16, -8($29)
 	lw	$31, -4($29)
 	jr	$31
-# Function isMul16
 isMul16:
 	sw	$31, -4($29)
 	addi	$29, $29, -8
-# 	ori	_param_a_17_,$2,0
-# 	ori	_divide_L_23_,_param_a_17_,0
 	ori	$3, $0, 16
-# was:	ori	_divide_R_24_, $0, 16
 	div	$4, $2, $3
-# was:	div	_times_L_21_, _divide_L_23_, _divide_R_24_
 	ori	$3, $0, 16
-# was:	ori	_times_R_22_, $0, 16
 	mul	$3, $4, $3
-# was:	mul	_eq_L_19_, _times_L_21_, _times_R_22_
-# 	ori	_eq_R_20_,_param_a_17_,0
 	ori	$4, $0, 0
-# was:	ori	_isMul16res_18_, $0, 0
 	bne	$3, $2, _false_25_
-# was:	bne	_eq_L_19_, _eq_R_20_, _false_25_
 	ori	$4, $0, 1
-# was:	ori	_isMul16res_18_, $0, 1
 _false_25_:
 	ori	$2, $4, 0
-# was:	ori	$2, _isMul16res_18_, 0
 	addi	$29, $29, 8
 	lw	$31, -4($29)
 	jr	$31
-# Function main
 main:
 	sw	$31, -4($29)
 	sw	$22, -32($29)
@@ -136,207 +86,108 @@ main:
 	sw	$16, -8($29)
 	addi	$29, $29, -36
 	jal	getint
-# was:	jal	getint, $2
-# 	ori	_letBind_27_,$2,0
-# 	ori	_size_reg_34_,_letBind_27_,0
 	bgez	$2, _safe_lab_35_
-# was:	bgez	_size_reg_34_, _safe_lab_35_
 	ori	$5, $0, 10
-# was:	ori	$5, $0, 10
 	la	$6, _Msg_IllegalArraySize_
-# was:	la	$6, _Msg_IllegalArraySize_
 	j	_RuntimeError_
 _safe_lab_35_:
 	ori	$7, $28, 0
-# was:	ori	_arr_reg_30_, $28, 0
 	sll	$3, $2, 2
-# was:	sll	_tmp_41_, _size_reg_34_, 2
 	addi	$3, $3, 4
-# was:	addi	_tmp_41_, _tmp_41_, 4
 	add	$28, $28, $3
-# was:	add	$28, $28, _tmp_41_
 	sw	$2, 0($7)
-# was:	sw	_size_reg_34_, 0(_arr_reg_30_)
 	addi	$3, $7, 4
-# was:	addi	_addr_reg_36_, _arr_reg_30_, 4
 	ori	$5, $0, 0
-# was:	ori	_i_reg_37_, $0, 0
 _loop_beg_38_:
 	sub	$4, $5, $2
-# was:	sub	_tmp_reg_40_, _i_reg_37_, _size_reg_34_
 	bgez	$4, _loop_end_39_
-# was:	bgez	_tmp_reg_40_, _loop_end_39_
 	sw	$5, 0($3)
-# was:	sw	_i_reg_37_, 0(_addr_reg_36_)
 	addi	$3, $3, 4
-# was:	addi	_addr_reg_36_, _addr_reg_36_, 4
 	addi	$5, $5, 1
-# was:	addi	_i_reg_37_, _i_reg_37_, 1
 	j	_loop_beg_38_
 _loop_end_39_:
 	lw	$3, 0($7)
-# was:	lw	_size_reg_29_, 0(_arr_reg_30_)
 	ori	$2, $28, 0
-# was:	ori	_letBind_28_, $28, 0
 	sll	$4, $3, 2
-# was:	sll	_tmp_57_, _size_reg_29_, 2
 	addi	$4, $4, 4
-# was:	addi	_tmp_57_, _tmp_57_, 4
 	add	$28, $28, $4
-# was:	add	$28, $28, _tmp_57_
 	sw	$3, 0($2)
-# was:	sw	_size_reg_29_, 0(_letBind_28_)
 	addi	$4, $2, 4
-# was:	addi	_addr_reg_42_, _letBind_28_, 4
 	ori	$6, $0, 0
-# was:	ori	_i_reg_43_, $0, 0
 	ori	$5, $0, 0
-# was:	ori	_j_reg_44_, $0, 0
 	addi	$7, $7, 4
-# was:	addi	_elem_reg_31_, _arr_reg_30_, 4
 _loop_beg_45_:
 	sub	$8, $6, $3
-# was:	sub	_tmp_reg_48_, _i_reg_43_, _size_reg_29_
 	bgez	$8, _loop_end_46_
-# was:	bgez	_tmp_reg_48_, _loop_end_46_
 	lw	$10, 0($7)
-# was:	lw	_res_reg_32_, 0(_elem_reg_31_)
 	addi	$7, $7, 4
-# was:	addi	_elem_reg_31_, _elem_reg_31_, 4
-# 	ori	_eq_L_50_,_res_reg_32_,0
 	ori	$9, $10, 0
-# was:	ori	_divide_L_54_, _res_reg_32_, 0
 	ori	$8, $0, 2
-# was:	ori	_divide_R_55_, $0, 2
 	div	$8, $9, $8
-# was:	div	_times_L_52_, _divide_L_54_, _divide_R_55_
 	ori	$9, $0, 2
-# was:	ori	_times_R_53_, $0, 2
 	mul	$9, $8, $9
-# was:	mul	_eq_R_51_, _times_L_52_, _times_R_53_
 	ori	$8, $0, 0
-# was:	ori	_fun_arg_res_49_, $0, 0
 	bne	$10, $9, _false_56_
-# was:	bne	_eq_L_50_, _eq_R_51_, _false_56_
 	ori	$8, $0, 1
-# was:	ori	_fun_arg_res_49_, $0, 1
 _false_56_:
-# 	ori	_bool_reg_33_,_fun_arg_res_49_,0
 	beq	$8, $0, _not_true_47_
-# was:	beq	_bool_reg_33_, $0, _not_true_47_
 	sw	$10, 0($4)
-# was:	sw	_res_reg_32_, 0(_addr_reg_42_)
 	addi	$5, $5, 1
-# was:	addi	_j_reg_44_, _j_reg_44_, 1
 	addi	$4, $4, 4
-# was:	addi	_addr_reg_42_, _addr_reg_42_, 4
 _not_true_47_:
 	addi	$6, $6, 1
-# was:	addi	_i_reg_43_, _i_reg_43_, 1
 	j	_loop_beg_45_
 _loop_end_46_:
 	sw	$5, 0($2)
-# was:	sw	_j_reg_44_, 0(_letBind_28_)
-# 	ori	_arr_reg_60_,_letBind_28_,0
 	lw	$5, 0($2)
-# was:	lw	_size_reg_59_, 0(_arr_reg_60_)
 	ori	$4, $28, 0
-# was:	ori	_letBind_58_, $28, 0
 	sll	$3, $5, 2
-# was:	sll	_tmp_71_, _size_reg_59_, 2
 	addi	$3, $3, 4
-# was:	addi	_tmp_71_, _tmp_71_, 4
 	add	$28, $28, $3
-# was:	add	$28, $28, _tmp_71_
 	sw	$5, 0($4)
-# was:	sw	_size_reg_59_, 0(_letBind_58_)
 	addi	$7, $4, 4
-# was:	addi	_addr_reg_63_, _letBind_58_, 4
 	ori	$6, $0, 0
-# was:	ori	_i_reg_64_, $0, 0
 	addi	$3, $2, 4
-# was:	addi	_elem_reg_61_, _arr_reg_60_, 4
 _loop_beg_65_:
 	sub	$2, $6, $5
-# was:	sub	_tmp_reg_67_, _i_reg_64_, _size_reg_59_
 	bgez	$2, _loop_end_66_
-# was:	bgez	_tmp_reg_67_, _loop_end_66_
 	lw	$2, 0($3)
-# was:	lw	_res_reg_62_, 0(_elem_reg_61_)
 	addi	$3, $3, 4
-# was:	addi	_elem_reg_61_, _elem_reg_61_, 4
 	ori	$8, $2, 0
-# was:	ori	_times_L_69_, _res_reg_62_, 0
-# 	ori	_times_R_70_,_res_reg_62_,0
 	mul	$2, $8, $2
-# was:	mul	_fun_arg_res_68_, _times_L_69_, _times_R_70_
-# 	ori	_res_reg_62_,_fun_arg_res_68_,0
 	sw	$2, 0($7)
-# was:	sw	_res_reg_62_, 0(_addr_reg_63_)
 	addi	$7, $7, 4
-# was:	addi	_addr_reg_63_, _addr_reg_63_, 4
 	addi	$6, $6, 1
-# was:	addi	_i_reg_64_, _i_reg_64_, 1
 	j	_loop_beg_65_
 _loop_end_66_:
-# 	ori	_arr_reg_74_,_letBind_58_,0
 	lw	$17, 0($4)
-# was:	lw	_size_reg_73_, 0(_arr_reg_74_)
 	ori	$16, $28, 0
-# was:	ori	_letBind_72_, $28, 0
 	sll	$2, $17, 2
-# was:	sll	_tmp_86_, _size_reg_73_, 2
 	addi	$2, $2, 4
-# was:	addi	_tmp_86_, _tmp_86_, 4
 	add	$28, $28, $2
-# was:	add	$28, $28, _tmp_86_
 	sw	$17, 0($16)
-# was:	sw	_size_reg_73_, 0(_letBind_72_)
 	addi	$19, $16, 4
-# was:	addi	_addr_reg_78_, _letBind_72_, 4
 	ori	$18, $0, 0
-# was:	ori	_i_reg_79_, $0, 0
 	ori	$20, $0, 0
-# was:	ori	_j_reg_80_, $0, 0
 	addi	$21, $4, 4
-# was:	addi	_elem_reg_75_, _arr_reg_74_, 4
 _loop_beg_81_:
 	sub	$2, $18, $17
-# was:	sub	_tmp_reg_84_, _i_reg_79_, _size_reg_73_
 	bgez	$2, _loop_end_82_
-# was:	bgez	_tmp_reg_84_, _loop_end_82_
 	lw	$22, 0($21)
-# was:	lw	_res_reg_76_, 0(_elem_reg_75_)
 	addi	$21, $21, 4
-# was:	addi	_elem_reg_75_, _elem_reg_75_, 4
 	ori	$2, $22, 0
-# was:	ori	$2, _res_reg_76_, 0
 	jal	isMul16
-# was:	jal	isMul16, $2
-# 	ori	_tmp_reg_85_,$2,0
-# 	ori	_bool_reg_77_,_tmp_reg_85_,0
 	beq	$2, $0, _not_true_83_
-# was:	beq	_bool_reg_77_, $0, _not_true_83_
 	sw	$22, 0($19)
-# was:	sw	_res_reg_76_, 0(_addr_reg_78_)
 	addi	$20, $20, 1
-# was:	addi	_j_reg_80_, _j_reg_80_, 1
 	addi	$19, $19, 4
-# was:	addi	_addr_reg_78_, _addr_reg_78_, 4
 _not_true_83_:
 	addi	$18, $18, 1
-# was:	addi	_i_reg_79_, _i_reg_79_, 1
 	j	_loop_beg_81_
 _loop_end_82_:
 	sw	$20, 0($16)
-# was:	sw	_j_reg_80_, 0(_letBind_72_)
 	ori	$2, $16, 0
-# was:	ori	_arg_87_, _letBind_72_, 0
-# 	ori	$2,_arg_87_,0
 	jal	write_int_arr
-# was:	jal	write_int_arr, $2
-# 	ori	_mainres_26_,$2,0
-# 	ori	$2,_mainres_26_,0
 	addi	$29, $29, 36
 	lw	$22, -32($29)
 	lw	$21, -28($29)
@@ -441,7 +292,6 @@ _RuntimeError_:
 	syscall
 	j	_stop_
 	.data	
-# Fixed strings for I/O
 _ErrMsg_:
 	.asciiz	"Runtime error at line "
 _colon_space_:
@@ -450,14 +300,12 @@ _cr_:
 	.asciiz	"\n"
 _space_:
 	.asciiz	" "
-# Message strings for specific errors
 _Msg_IllegalArraySize_:
 	.asciiz	"negative array size"
 _Msg_IllegalIndex_:
 	.asciiz	"array index out of bounds"
 _Msg_DivZero_:
 	.asciiz	"division by zero"
-# String Literals
 	.align	2
 _true:
 	.space	4
diff --git a/tests/inline_map.asm b/tests/inline_map.asm
index 1751fb3..e172194 100644
--- a/tests/inline_map.asm
+++ b/tests/inline_map.asm
@@ -92,9 +92,11 @@ write_int_arr:
 	sw	$16, -8($29)
 	addi	$29, $29, -28
 # 	ori	_param_x_16_,$2,0
+# map
 # 	ori	_arr_reg_19_,_param_x_16_,0
 	lw	$16, 0($2)
 # was:	lw	_size_reg_18_, 0(_arr_reg_19_)
+# dynalloc
 	ori	$17, $28, 0
 # was:	ori	_write_int_arrres_17_, $28, 0
 	sll	$3, $16, 2
@@ -154,12 +156,14 @@ boo:
 	addi	$29, $29, -28
 # 	ori	_param_a_29_,$2,0
 	ori	$0, $0, 8
-# was:	ori	_letBind_31_, $0, 8
+# was:	ori	_letBind_32_, $0, 8
+# map
 # 	ori	_arr_reg_34_,_param_a_29_,0
 	lw	$17, 0($2)
 # was:	lw	_size_reg_33_, 0(_arr_reg_34_)
+# dynalloc
 	ori	$16, $28, 0
-# was:	ori	_letBind_32_, $28, 0
+# was:	ori	_letBind_31_, $28, 0
 	sll	$3, $17, 2
 # was:	sll	_tmp_43_, _size_reg_33_, 2
 	addi	$3, $3, 4
@@ -167,9 +171,9 @@ boo:
 	add	$28, $28, $3
 # was:	add	$28, $28, _tmp_43_
 	sw	$17, 0($16)
-# was:	sw	_size_reg_33_, 0(_letBind_32_)
+# was:	sw	_size_reg_33_, 0(_letBind_31_)
 	addi	$18, $16, 4
-# was:	addi	_addr_reg_37_, _letBind_32_, 4
+# was:	addi	_addr_reg_37_, _letBind_31_, 4
 	ori	$19, $0, 0
 # was:	ori	_i_reg_38_, $0, 0
 	addi	$20, $2, 4
@@ -197,7 +201,7 @@ _loop_beg_39_:
 	j	_loop_beg_39_
 _loop_end_40_:
 	ori	$2, $16, 0
-# was:	ori	_boores_30_, _letBind_32_, 0
+# was:	ori	_boores_30_, _letBind_31_, 0
 # 	ori	$2,_boores_30_,0
 	addi	$29, $29, 28
 	lw	$20, -24($29)
@@ -218,10 +222,10 @@ main:
 	addi	$29, $29, -28
 	jal	getint
 # was:	jal	getint, $2
-	ori	$5, $2, 0
+	ori	$3, $2, 0
 # was:	ori	_letBind_45_, $2, 0
 # 	ori	_size_reg_47_,_letBind_45_,0
-	bgez	$5, _safe_lab_48_
+	bgez	$3, _safe_lab_48_
 # was:	bgez	_size_reg_47_, _safe_lab_48_
 	ori	$5, $0, 15
 # was:	ori	$5, $0, 15
@@ -229,72 +233,75 @@ main:
 # was:	la	$6, _Msg_IllegalArraySize_
 	j	_RuntimeError_
 _safe_lab_48_:
-	ori	$3, $28, 0
+# dynalloc
+	ori	$2, $28, 0
 # was:	ori	_letBind_46_, $28, 0
-	sll	$2, $5, 2
+	sll	$4, $3, 2
 # was:	sll	_tmp_54_, _size_reg_47_, 2
-	addi	$2, $2, 4
+	addi	$4, $4, 4
 # was:	addi	_tmp_54_, _tmp_54_, 4
-	add	$28, $28, $2
+	add	$28, $28, $4
 # was:	add	$28, $28, _tmp_54_
-	sw	$5, 0($3)
+	sw	$3, 0($2)
 # was:	sw	_size_reg_47_, 0(_letBind_46_)
-	addi	$3, $3, 4
+	addi	$5, $2, 4
 # was:	addi	_addr_reg_49_, _letBind_46_, 4
-	ori	$4, $0, 0
+	ori	$6, $0, 0
 # was:	ori	_i_reg_50_, $0, 0
 _loop_beg_51_:
-	sub	$2, $4, $5
+	sub	$4, $6, $3
 # was:	sub	_tmp_reg_53_, _i_reg_50_, _size_reg_47_
-	bgez	$2, _loop_end_52_
+	bgez	$4, _loop_end_52_
 # was:	bgez	_tmp_reg_53_, _loop_end_52_
-	sw	$4, 0($3)
+	sw	$6, 0($5)
 # was:	sw	_i_reg_50_, 0(_addr_reg_49_)
-	addi	$3, $3, 4
+	addi	$5, $5, 4
 # was:	addi	_addr_reg_49_, _addr_reg_49_, 4
-	addi	$4, $4, 1
+	addi	$6, $6, 1
 # was:	addi	_i_reg_50_, _i_reg_50_, 1
 	j	_loop_beg_51_
 _loop_end_52_:
-# 	ori	_plus_L_56_,_letBind_45_,0
-	ori	$2, $5, 0
-# was:	ori	_plus_R_57_, _letBind_45_, 0
-	add	$2, $5, $2
-# was:	add	_letBind_55_, _plus_L_56_, _plus_R_57_
-# 	ori	_plus_L_61_,_letBind_45_,0
-	ori	$3, $5, 0
-# was:	ori	_plus_R_62_, _letBind_45_, 0
-	add	$3, $5, $3
+# 	ori	_plus_L_57_,_letBind_45_,0
+	ori	$4, $3, 0
+# was:	ori	_plus_R_58_, _letBind_45_, 0
+	add	$0, $3, $4
+# was:	add	_letBind_56_, _plus_L_57_, _plus_R_58_
+	ori	$4, $3, 0
+# was:	ori	_plus_L_61_, _letBind_45_, 0
+# 	ori	_plus_R_62_,_letBind_45_,0
+	add	$4, $4, $3
 # was:	add	_plus_L_59_, _plus_L_61_, _plus_R_62_
 # 	ori	_plus_R_60_,_letBind_45_,0
-	add	$0, $3, $5
-# was:	add	_letBind_58_, _plus_L_59_, _plus_R_60_
-# 	ori	_arg_64_,_letBind_55_,0
+	add	$0, $4, $3
+# was:	add	_letBind_55_, _plus_L_59_, _plus_R_60_
+# 	ori	_arg_64_,_letBind_46_,0
 # 	ori	$2,_arg_64_,0
 	jal	boo
 # was:	jal	boo, $2
 # 	ori	_letBind_63_,$2,0
+# map
 # 	ori	_arr_reg_67_,_letBind_63_,0
-	lw	$17, 0($2)
+	lw	$16, 0($2)
 # was:	lw	_size_reg_66_, 0(_arr_reg_67_)
-	ori	$16, $28, 0
+# dynalloc
+	ori	$17, $28, 0
 # was:	ori	_letBind_65_, $28, 0
-	sll	$3, $17, 2
+	sll	$3, $16, 2
 # was:	sll	_tmp_76_, _size_reg_66_, 2
 	addi	$3, $3, 4
 # was:	addi	_tmp_76_, _tmp_76_, 4
 	add	$28, $28, $3
 # was:	add	$28, $28, _tmp_76_
-	sw	$17, 0($16)
+	sw	$16, 0($17)
 # was:	sw	_size_reg_66_, 0(_letBind_65_)
-	addi	$18, $16, 4
+	addi	$18, $17, 4
 # was:	addi	_addr_reg_70_, _letBind_65_, 4
 	ori	$19, $0, 0
 # was:	ori	_i_reg_71_, $0, 0
 	addi	$20, $2, 4
 # was:	addi	_elem_reg_68_, _arr_reg_67_, 4
 _loop_beg_72_:
-	sub	$2, $19, $17
+	sub	$2, $19, $16
 # was:	sub	_tmp_reg_74_, _i_reg_71_, _size_reg_66_
 	bgez	$2, _loop_end_73_
 # was:	bgez	_tmp_reg_74_, _loop_end_73_
@@ -315,7 +322,7 @@ _loop_beg_72_:
 # was:	addi	_i_reg_71_, _i_reg_71_, 1
 	j	_loop_beg_72_
 _loop_end_73_:
-	ori	$2, $16, 0
+	ori	$2, $17, 0
 # was:	ori	_arg_77_, _letBind_65_, 0
 # 	ori	$2,_arg_77_,0
 	jal	write_int_arr
diff --git a/tests/io_mssp.asm b/tests/io_mssp.asm
index 9c682bb..aa9fc3b 100644
--- a/tests/io_mssp.asm
+++ b/tests/io_mssp.asm
@@ -117,6 +117,7 @@ read_int_arr:
 # was:	la	$6, _Msg_IllegalArraySize_
 	j	_RuntimeError_
 _safe_lab_19_:
+# dynalloc
 	ori	$3, $28, 0
 # was:	ori	_letBind_17_, $28, 0
 	sll	$4, $2, 2
@@ -144,10 +145,12 @@ _loop_beg_22_:
 # was:	addi	_i_reg_21_, _i_reg_21_, 1
 	j	_loop_beg_22_
 _loop_end_23_:
+# map
 	ori	$2, $3, 0
 # was:	ori	_arr_reg_27_, _letBind_17_, 0
 	lw	$17, 0($2)
 # was:	lw	_size_reg_26_, 0(_arr_reg_27_)
+# dynalloc
 	ori	$16, $28, 0
 # was:	ori	_read_int_arrres_16_, $28, 0
 	sll	$3, $17, 2
@@ -232,10 +235,12 @@ write_int_arr:
 # 	ori	$2,_tmp_43_,0
 	jal	putstring
 # was:	jal	putstring, $2
+# map
 	ori	$2, $16, 0
 # was:	ori	_arr_reg_47_, _param_arr_40_, 0
 	lw	$16, 0($2)
 # was:	lw	_size_reg_46_, 0(_arr_reg_47_)
+# dynalloc
 	ori	$3, $28, 0
 # was:	ori	_letBind_45_, $28, 0
 	sll	$4, $16, 2
@@ -333,6 +338,7 @@ mapper:
 # 	ori	_letBind_71_,$2,0
 	ori	$5, $0, 4
 # was:	ori	_size_reg_74_, $0, 4
+# dynalloc
 	ori	$3, $28, 0
 # was:	ori	_mapperres_70_, $28, 0
 	sll	$4, $5, 2
@@ -717,6 +723,7 @@ _safe_lab_172_:
 # was:	add	_letBind_158_, _plus_L_159_, _plus_R_160_
 	ori	$6, $0, 4
 # was:	ori	_size_reg_173_, $0, 4
+# dynalloc
 	ori	$5, $28, 0
 # was:	ori	_reducerres_80_, $28, 0
 	sll	$4, $6, 2
@@ -776,9 +783,11 @@ mssp:
 	jal	read_int_arr
 # was:	jal	read_int_arr, $2
 # 	ori	_letBind_179_,$2,0
+# map
 # 	ori	_arr_reg_183_,_letBind_179_,0
 	lw	$17, 0($2)
 # was:	lw	_size_reg_182_, 0(_arr_reg_183_)
+# dynalloc
 	ori	$16, $28, 0
 # was:	ori	_letBind_181_, $28, 0
 	sll	$3, $17, 2
@@ -819,6 +828,7 @@ _loop_beg_188_:
 _loop_end_189_:
 	ori	$3, $0, 4
 # was:	ori	_size_reg_194_, $0, 4
+# dynalloc
 	ori	$2, $28, 0
 # was:	ori	_letBind_193_, $28, 0
 	sll	$4, $3, 2
diff --git a/tests/iota.asm b/tests/iota.asm
index dd71444..ee888e2 100644
--- a/tests/iota.asm
+++ b/tests/iota.asm
@@ -32,6 +32,7 @@ main:
 # was:	la	$6, _Msg_IllegalArraySize_
 	j	_RuntimeError_
 _safe_lab_4_:
+# dynalloc
 	ori	$16, $28, 0
 # was:	ori	_letBind_2_, $28, 0
 	sll	$3, $2, 2
diff --git a/tests/lambda.asm b/tests/lambda.asm
index 4b54603..cb894b7 100644
--- a/tests/lambda.asm
+++ b/tests/lambda.asm
@@ -52,9 +52,11 @@ write_int_arr:
 	sw	$16, -8($29)
 	addi	$29, $29, -28
 # 	ori	_param_x_4_,$2,0
+# map
 # 	ori	_arr_reg_7_,_param_x_4_,0
 	lw	$16, 0($2)
 # was:	lw	_size_reg_6_, 0(_arr_reg_7_)
+# dynalloc
 	ori	$17, $28, 0
 # was:	ori	_write_int_arrres_5_, $28, 0
 	sll	$3, $16, 2
@@ -121,6 +123,7 @@ main:
 # was:	la	$6, _Msg_IllegalArraySize_
 	j	_RuntimeError_
 _safe_lab_21_:
+# dynalloc
 	ori	$6, $28, 0
 # was:	ori	_letBind_19_, $28, 0
 	sll	$2, $5, 2
@@ -148,9 +151,11 @@ _loop_beg_24_:
 # was:	addi	_i_reg_23_, _i_reg_23_, 1
 	j	_loop_beg_24_
 _loop_end_25_:
+# map
 # 	ori	_arr_reg_31_,_letBind_19_,0
 	lw	$2, 0($6)
 # was:	lw	_size_reg_30_, 0(_arr_reg_31_)
+# dynalloc
 	ori	$3, $28, 0
 # was:	ori	_arg_29_, $28, 0
 	sll	$4, $2, 2
diff --git a/tests/map_red_io.asm b/tests/map_red_io.asm
index 5f78a5e..8c3cc07 100644
--- a/tests/map_red_io.asm
+++ b/tests/map_red_io.asm
@@ -121,6 +121,7 @@ main:
 # was:	la	$6, _Msg_IllegalArraySize_
 	j	_RuntimeError_
 _safe_lab_25_:
+# dynalloc
 	ori	$16, $28, 0
 # was:	ori	_letBind_23_, $28, 0
 	sll	$3, $2, 2
@@ -148,9 +149,11 @@ _loop_beg_28_:
 # was:	addi	_i_reg_27_, _i_reg_27_, 1
 	j	_loop_beg_28_
 _loop_end_29_:
+# map
 # 	ori	_arr_reg_34_,_letBind_23_,0
 	lw	$17, 0($16)
 # was:	lw	_size_reg_33_, 0(_arr_reg_34_)
+# dynalloc
 	ori	$20, $28, 0
 # was:	ori	_letBind_32_, $28, 0
 	sll	$2, $17, 2
@@ -219,10 +222,12 @@ _loop_beg_49_:
 # was:	addi	_ind_var_47_, _ind_var_47_, 1
 	j	_loop_beg_49_
 _loop_end_50_:
+# map
 	ori	$2, $16, 0
 # was:	ori	_arr_reg_54_, _letBind_23_, 0
 	lw	$18, 0($2)
 # was:	lw	_size_reg_53_, 0(_arr_reg_54_)
+# dynalloc
 	ori	$16, $28, 0
 # was:	ori	_letBind_52_, $28, 0
 	addi	$3, $18, 3
diff --git a/tests/ordchr.asm b/tests/ordchr.asm
index 0b061c3..dba29e0 100644
--- a/tests/ordchr.asm
+++ b/tests/ordchr.asm
@@ -39,6 +39,7 @@ read_string:
 	sw	$16, -8($29)
 	addi	$29, $29, -28
 # 	ori	_param_n_3_,$2,0
+# map
 	ori	$3, $2, 0
 # was:	ori	_size_reg_9_, _param_n_3_, 0
 	bgez	$3, _safe_lab_10_
@@ -49,6 +50,7 @@ read_string:
 # was:	la	$6, _Msg_IllegalArraySize_
 	j	_RuntimeError_
 _safe_lab_10_:
+# dynalloc
 	ori	$2, $28, 0
 # was:	ori	_arr_reg_6_, $28, 0
 	sll	$4, $3, 2
@@ -78,6 +80,7 @@ _loop_beg_13_:
 _loop_end_14_:
 	lw	$16, 0($2)
 # was:	lw	_size_reg_5_, 0(_arr_reg_6_)
+# dynalloc
 	ori	$17, $28, 0
 # was:	ori	_read_stringres_4_, $28, 0
 	addi	$3, $16, 3
@@ -161,9 +164,13 @@ main:
 	jal	read_string
 # was:	jal	read_string, $2
 # 	ori	_letBind_30_,$2,0
+# map
+# map
+# map
 # 	ori	_arr_reg_42_,_letBind_30_,0
 	lw	$18, 0($2)
 # was:	lw	_size_reg_41_, 0(_arr_reg_42_)
+# dynalloc
 	ori	$20, $28, 0
 # was:	ori	_arr_reg_38_, $28, 0
 	sll	$3, $18, 2
@@ -204,6 +211,7 @@ _loop_beg_47_:
 _loop_end_48_:
 	lw	$19, 0($20)
 # was:	lw	_size_reg_37_, 0(_arr_reg_38_)
+# dynalloc
 	ori	$16, $28, 0
 # was:	ori	_arr_reg_34_, $28, 0
 	sll	$2, $19, 2
@@ -244,6 +252,7 @@ _loop_beg_54_:
 _loop_end_55_:
 	lw	$18, 0($16)
 # was:	lw	_size_reg_33_, 0(_arr_reg_34_)
+# dynalloc
 	ori	$17, $28, 0
 # was:	ori	_letBind_32_, $28, 0
 	addi	$2, $18, 3
diff --git a/tests/proj_figure3.asm b/tests/proj_figure3.asm
index 202498c..b9c882e 100644
--- a/tests/proj_figure3.asm
+++ b/tests/proj_figure3.asm
@@ -67,6 +67,7 @@ main:
 # was:	la	$6, _Msg_IllegalArraySize_
 	j	_RuntimeError_
 _safe_lab_14_:
+# dynalloc
 	ori	$20, $28, 0
 # was:	ori	_letBind_12_, $28, 0
 	sll	$3, $2, 2
@@ -94,9 +95,11 @@ _loop_beg_17_:
 # was:	addi	_i_reg_16_, _i_reg_16_, 1
 	j	_loop_beg_17_
 _loop_end_18_:
+# map
 # 	ori	_arr_reg_23_,_letBind_12_,0
 	lw	$17, 0($20)
 # was:	lw	_size_reg_22_, 0(_arr_reg_23_)
+# dynalloc
 	ori	$16, $28, 0
 # was:	ori	_letBind_21_, $28, 0
 	sll	$2, $17, 2
@@ -163,10 +166,12 @@ _loop_beg_38_:
 # was:	addi	_ind_var_36_, _ind_var_36_, 1
 	j	_loop_beg_38_
 _loop_end_39_:
+# map
 	ori	$2, $16, 0
 # was:	ori	_arr_reg_43_, _letBind_21_, 0
 	lw	$16, 0($2)
 # was:	lw	_size_reg_42_, 0(_arr_reg_43_)
+# dynalloc
 	ori	$17, $28, 0
 # was:	ori	_letBind_41_, $28, 0
 	addi	$3, $16, 3
diff --git a/tests/reduce.asm b/tests/reduce.asm
index 4323dc3..49495b9 100644
--- a/tests/reduce.asm
+++ b/tests/reduce.asm
@@ -40,6 +40,7 @@ main:
 	addi	$29, $29, -20
 	ori	$3, $0, 3
 # was:	ori	_size_reg_14_, $0, 3
+# dynalloc
 	ori	$16, $28, 0
 # was:	ori	_arr_reg_8_, $28, 0
 	sll	$2, $3, 2
diff --git a/tests/replicate.asm b/tests/replicate.asm
index 5291a7a..0140378 100644
--- a/tests/replicate.asm
+++ b/tests/replicate.asm
@@ -62,6 +62,7 @@ main:
 # was:	la	$6, _Msg_IllegalArraySize_
 	j	_RuntimeError_
 _safe_lab_9_:
+# dynalloc
 	ori	$3, $28, 0
 # was:	ori	_letBind_6_, $28, 0
 	sll	$4, $2, 2
@@ -89,9 +90,11 @@ _loop_beg_12_:
 # was:	addi	_i_reg_11_, _i_reg_11_, 1
 	j	_loop_beg_12_
 _loop_end_13_:
+# map
 # 	ori	_arr_reg_17_,_letBind_6_,0
 	lw	$16, 0($3)
 # was:	lw	_size_reg_16_, 0(_arr_reg_17_)
+# dynalloc
 	ori	$17, $28, 0
 # was:	ori	_mainres_5_, $28, 0
 	addi	$2, $16, 3
diff --git a/tests/scan.asm b/tests/scan.asm
index 99def1b..0237959 100644
--- a/tests/scan.asm
+++ b/tests/scan.asm
@@ -61,6 +61,7 @@ main:
 	addi	$29, $29, -28
 	ori	$2, $0, 3
 # was:	ori	_size_reg_11_, $0, 3
+# dynalloc
 	ori	$3, $28, 0
 # was:	ori	_letBind_10_, $28, 0
 	sll	$4, $2, 2
@@ -96,6 +97,7 @@ main:
 # was:	ori	_nelem_reg_20_, $0, 0
 	lw	$17, 0($3)
 # was:	lw	_size_reg_16_, 0(_arr_reg_17_)
+# dynalloc
 	ori	$16, $28, 0
 # was:	ori	_letBind_15_, $28, 0
 	sll	$4, $17, 2
@@ -135,10 +137,12 @@ _loop_beg_23_:
 # was:	addi	_i_reg_22_, _i_reg_22_, 1
 	j	_loop_beg_23_
 _loop_end_24_:
+# map
 	ori	$2, $16, 0
 # was:	ori	_arr_reg_29_, _letBind_15_, 0
 	lw	$16, 0($2)
 # was:	lw	_size_reg_28_, 0(_arr_reg_29_)
+# dynalloc
 	ori	$17, $28, 0
 # was:	ori	_mainres_9_, $28, 0
 	sll	$3, $16, 2
diff --git a/tests/short_circuit.asm b/tests/short_circuit.asm
index f14398d..40c2437 100644
--- a/tests/short_circuit.asm
+++ b/tests/short_circuit.asm
@@ -35,40 +35,33 @@ main:
 	addi	$29, $29, -12
 	ori	$3, $0, 0
 # was:	ori	_tmp_4_, $0, 0
-	beq	$3, $16, _false_5_
-# was:	beq	_tmp_4_, 0, _false_5_
-	jal	no_way
-# was:	jal	no_way, 
-	ori	$3, $2, 0
-# was:	ori	_tmp_4_, $2, 0
-_false_5_:
 # 	ori	_letBind_3_,_tmp_4_,0
 	la	$2, _true
 # was:	la	$2, _true
-	bne	$3, $0, _wBoolF_6_
-# was:	bne	_letBind_3_, $0, _wBoolF_6_
+	bne	$3, $0, _wBoolF_5_
+# was:	bne	_letBind_3_, $0, _wBoolF_5_
 	la	$2, _false
 # was:	la	$2, _false
-_wBoolF_6_:
+_wBoolF_5_:
 	jal	putstring
 # was:	jal	putstring, $2
 	ori	$3, $0, 1
-# was:	ori	_tmp_8_, $0, 1
-	bne	$3, $16, _true_9_
-# was:	bne	_tmp_8_, 0, _true_9_
+# was:	ori	_tmp_7_, $0, 1
+	bne	$3, $16, _true_8_
+# was:	bne	_tmp_7_, 0, _true_8_
 	jal	no_way
 # was:	jal	no_way, 
 	ori	$3, $2, 0
-# was:	ori	_tmp_8_, $2, 0
-_true_9_:
-# 	ori	_letBind_7_,_tmp_8_,0
+# was:	ori	_tmp_7_, $2, 0
+_true_8_:
+# 	ori	_letBind_6_,_tmp_7_,0
 	la	$2, _true
 # was:	la	$2, _true
-	bne	$3, $0, _wBoolF_10_
-# was:	bne	_letBind_7_, $0, _wBoolF_10_
+	bne	$3, $0, _wBoolF_9_
+# was:	bne	_letBind_6_, $0, _wBoolF_9_
 	la	$2, _false
 # was:	la	$2, _false
-_wBoolF_10_:
+_wBoolF_9_:
 	jal	putstring
 # was:	jal	putstring, $2
 	ori	$2, $0, 1