From 3cce70432d01f8ce07853a060144af01a112da59 Mon Sep 17 00:00:00 2001
From: NikolajDanger <nikolajgade@live.dk>
Date: Wed, 25 May 2022 16:01:54 +0200
Subject: [PATCH] :sparkles:

---
 Fasto/CodeGen.fs          | 162 +++++++++-
 Fasto/TypeChecker.fs      |  14 +-
 tests/filter-on-2darr.asm | 642 +++++++++++++++++++++-----------------
 tests/filter.asm          | 554 +++++++++++++++++---------------
 tests/replicate.asm       | 165 +++++-----
 tests/scan.asm            | 265 +++++++++-------
 6 files changed, 1048 insertions(+), 754 deletions(-)

diff --git a/Fasto/CodeGen.fs b/Fasto/CodeGen.fs
index b46144b..ac8efbd 100644
--- a/Fasto/CodeGen.fs
+++ b/Fasto/CodeGen.fs
@@ -613,8 +613,59 @@ let rec compileExp  (e      : TypedExp)
         If `n` is less than `0` then remember to terminate the program with
         an error -- see implementation of `iota`.
   *)
-  | Replicate (_, _, _, _) ->
-      failwith "Unimplemented code generation of replicate"
+  | Replicate (n_exp, a_exp, a_type, (line, _)) ->
+      let a_size = getElemSize a_type
+
+      let size_reg = newReg "size_reg"
+      let n_code = compileExp n_exp vtable size_reg
+      (* size_reg is now the integer n. *)
+
+      let a_reg = newReg "a_reg"
+      let a_code = compileExp a_exp vtable a_reg
+
+      (* Check that array size N >= 0:
+         if N >= 0 then jumpto safe_lab
+         jumpto "_IllegalArrSizeError_"
+         safe_lab: ...
+      *)
+      let safe_lab = newLab "safe_lab"
+      let checksize = [ Mips.BGEZ (size_reg, safe_lab)
+                      ; Mips.LI (RN5, line)
+                      ; Mips.LA (RN6, "_Msg_IllegalArraySize_")
+                      ; Mips.J "_RuntimeError_"
+                      ; Mips.LABEL (safe_lab)
+                      ]
+
+      let addr_reg = newReg "addr_reg"
+      let i_reg = newReg "i_reg"
+      let init_regs = [ Mips.ADDI (addr_reg, place, 4)
+                      ; Mips.MOVE (i_reg, RZ) ]
+      (* addr_reg is now the position of the first array element. *)
+
+      (* Run a loop.  Keep jumping back to loop_beg until it is not the
+         case that i_reg < size_reg, and then jump to loop_end. *)
+      let loop_beg = newLab "loop_beg"
+      let loop_end = newLab "loop_end"
+      let tmp_reg = newReg "tmp_reg"
+      let loop_header = [ Mips.LABEL (loop_beg)
+                        ; Mips.SUB (tmp_reg, i_reg, size_reg)
+                        ; Mips.BGEZ (tmp_reg, loop_end)
+                        ]
+      (* 'arr[i] = a' *)
+      let loop_replicate  = [ mipsStore a_size (a_reg, addr_reg, 0) ]
+      let loop_footer     = [ Mips.ADDI (addr_reg, addr_reg, 4)
+                            ; Mips.ADDI (i_reg, i_reg, 1)
+                            ; Mips.J loop_beg
+                            ; Mips.LABEL loop_end
+                            ]
+      n_code
+       @ a_code
+       @ checksize
+       @ dynalloc (size_reg, place, Int)
+       @ init_regs
+       @ loop_header
+       @ loop_replicate
+       @ loop_footer
 
   (* TODO project task 2: see also the comment to replicate.
      (a) `filter(f, arr)`:  has some similarity with the implementation of map.
@@ -631,8 +682,59 @@ let rec compileExp  (e      : TypedExp)
          counter computed in step (c). You do this of course with a
          `Mips.SW(counter_reg, place, 0)` instruction.
   *)
-  | Filter (_, _, _, _) ->
-      failwith "Unimplemented code generation of filter"
+  | Filter (farg, arr_exp, a_type, pos) ->
+      let size_reg = newReg "size_reg" (* size of input/output array *)
+      let arr_reg  = newReg "arr_reg" (* address of array *)
+      let elem_reg = newReg "elem_reg" (* address of single element *)
+      let res_reg = newReg "res_reg"
+      let bool_reg = newReg "bool_reg"
+      let arr_code = compileExp arr_exp vtable arr_reg
+
+      let get_size = [ Mips.LW (size_reg, arr_reg, 0) ]
+
+      let addr_reg = newReg "addr_reg" (* address of element in new array *)
+      let i_reg = newReg "i_reg"
+      let j_reg = newReg "j_reg"
+      let init_regs = [ Mips.ADDI (addr_reg, place, 4)
+                      ; Mips.MOVE (i_reg, RZ)
+                      ; Mips.MOVE (j_reg, RZ)
+                      ; Mips.ADDI (elem_reg, arr_reg, 4)
+                      ]
+      let loop_beg = newLab "loop_beg"
+      let loop_end = newLab "loop_end"
+      let not_true = newLab "not_true"
+      let tmp_reg = newReg "tmp_reg"
+      let loop_header = [ Mips.LABEL (loop_beg)
+                        ; Mips.SUB (tmp_reg, i_reg, size_reg)
+                        ; Mips.BGEZ (tmp_reg, loop_end) ]
+      (* map is 'arr[i] = f(old_arr[i])'. *)
+      let a_size = getElemSize a_type
+      let loop_map =
+             [ mipsLoad a_size (res_reg, elem_reg, 0)
+             ; Mips.ADDI(elem_reg, elem_reg, elemSizeToInt a_size)
+             ]
+             @ applyFunArg(farg, [res_reg], vtable, bool_reg, pos)
+             @
+             [ Mips.BEQ (bool_reg, RZ, not_true)
+             ; mipsStore a_size (res_reg, addr_reg, 0)
+             ; Mips.ADDI (j_reg, j_reg, 1)
+             ; Mips.ADDI (addr_reg, addr_reg, elemSizeToInt a_size)
+             ]
+
+      let loop_footer =
+              [ Mips.LABEL not_true
+              ; Mips.ADDI (i_reg, i_reg, 1)
+              ; Mips.J loop_beg
+              ; Mips.LABEL loop_end
+              ; Mips.SW (j_reg,place,0)
+              ]
+      arr_code
+       @ get_size
+       @ dynalloc (size_reg, place, a_type)
+       @ init_regs
+       @ loop_header
+       @ loop_map
+       @ loop_footer
 
   (* TODO project task 2: see also the comment to replicate.
      `scan(f, ne, arr)`: you can inspire yourself from the implementation of
@@ -641,8 +743,56 @@ let rec compileExp  (e      : TypedExp)
         the current location of the result iterator at every iteration of
         the loop.
   *)
-  | Scan (_, _, _, _, _) ->
-      failwith "Unimplemented code generation of scan"
+  | Scan (farg, e_exp, arr_exp, a_type, pos) ->
+      let size_reg = newReg "size_reg" (* size of input/output array *)
+      let arr_reg  = newReg "arr_reg" (* address of array *)
+      let elem_reg = newReg "elem_reg" (* address of single element *)
+      let res_reg = newReg "res_reg"
+      let nelem_reg = newReg "nelem_reg"
+
+      let arr_code = compileExp arr_exp vtable arr_reg
+
+      let e_code = compileExp e_exp vtable nelem_reg
+
+      let get_size = [ Mips.LW (size_reg, arr_reg, 0) ]
+
+      let addr_reg = newReg "addr_reg" (* address of element in new array *)
+      let i_reg = newReg "i_reg"
+      let init_regs = [ Mips.ADDI (addr_reg, place, 4)
+                      ; Mips.MOVE (i_reg, RZ)
+                      ; Mips.ADDI (elem_reg, arr_reg, 4)
+                      ]
+      let loop_beg = newLab "loop_beg"
+      let loop_end = newLab "loop_end"
+      let tmp_reg = newReg "tmp_reg"
+      let loop_header = [ Mips.LABEL (loop_beg)
+                        ; Mips.SUB (tmp_reg, i_reg, size_reg)
+                        ; Mips.BGEZ (tmp_reg, loop_end) ]
+      (* map is 'arr[i] = f(old_arr[i])'. *)
+      let a_size = getElemSize a_type
+      let loop_map =
+             [ mipsLoad a_size (res_reg, elem_reg, 0)
+             ; Mips.ADDI(elem_reg, elem_reg, elemSizeToInt a_size)
+             ]
+             @ applyFunArg(farg, [nelem_reg ; res_reg], vtable, nelem_reg, pos)
+             @
+             [ mipsStore a_size (nelem_reg, addr_reg, 0)
+             ; Mips.ADDI (addr_reg, addr_reg, elemSizeToInt a_size)
+             ]
+
+      let loop_footer =
+              [ Mips.ADDI (i_reg, i_reg, 1)
+              ; Mips.J loop_beg
+              ; Mips.LABEL loop_end
+              ]
+      arr_code
+       @ e_code
+       @ get_size
+       @ dynalloc (size_reg, place, a_type)
+       @ init_regs
+       @ loop_header
+       @ loop_map
+       @ loop_footer
 
 and applyFunArg ( ff     : TypedFunArg
                 , args   : Mips.reg list
diff --git a/Fasto/TypeChecker.fs b/Fasto/TypeChecker.fs
index db90cb8..6dfd2ab 100644
--- a/Fasto/TypeChecker.fs
+++ b/Fasto/TypeChecker.fs
@@ -325,16 +325,18 @@ and checkExp  (ftab : FunTable)
         let elem_type =
             match arr_type with
               | Array t -> t
-              | _ -> reportTypeWrongKind "second argument of map" "array" arr_type pos
+              | _ -> reportTypeWrongKind "second argument of filter" "array" arr_type pos
         let (f', f_res_type, f_arg_type) =
             match checkFunArg ftab vtab pos f with
               | (f', res, [a1]) -> (f', res, a1)
               | (_, res, args) ->
-                   reportArityWrong "first argument of map" 1 (args,res) pos
+                   reportArityWrong "first argument of filter" 1 (args,res) pos
+        if not (f_res_type = Bool) then
+          reportTypesDifferent "function return-type not bool in filter" f_res_type Bool pos
         if elem_type <> f_arg_type then
-          reportTypesDifferent "function-argument and array-element types in map"
-                               f_arg_type elem_type pos
-        (Array f_res_type, Map (f', arr_exp_dec, elem_type, f_res_type, pos))
+          reportTypesDifferent "function-argument and array-element types in filter" f_arg_type elem_type pos
+
+        (Array f_arg_type, Filter (f', arr_exp_dec, elem_type, pos))
 
     (* TODO project task 2: `scan(f, ne, arr)`
         Hint: Implementation is very similar to `reduce(f, ne, arr)`.
@@ -367,7 +369,7 @@ and checkExp  (ftab : FunTable)
         if e_type <> f_argres_type then
           reportTypesDifferent "operation and start-element types in scan"
                                f_argres_type e_type pos
-        (f_argres_type, Reduce (f', e_dec, arr_dec, elem_type, pos))
+        (Array f_argres_type, Scan (f', e_dec, arr_dec, elem_type, pos))
 
 and checkFunArg  (ftab : FunTable)
                  (vtab : VarTable)
diff --git a/tests/filter-on-2darr.asm b/tests/filter-on-2darr.asm
index a19d18c..04c3955 100644
--- a/tests/filter-on-2darr.asm
+++ b/tests/filter-on-2darr.asm
@@ -17,337 +17,397 @@
 _stop_:
 	ori	$2, $0, 10
 	syscall
+# Function write_int
+write_int:
+	sw	$31, -4($29)
+	sw	$16, -8($29)
+	addi	$29, $29, -12
+# 	ori	_param_x_1_,$2,0
+	ori	$16, $2, 0
+# was:	ori	_tmp_3_, _param_x_1_, 0
+# 	ori	_write_intres_2_,_tmp_3_,0
+	ori	$2, $16, 0
+# was:	ori	$2, _write_intres_2_, 0
+	jal	putint
+# was:	jal	putint, $2
+	ori	$2, $16, 0
+# was:	ori	$2, _write_intres_2_, 0
+	addi	$29, $29, 12
+	lw	$16, -8($29)
+	lw	$31, -4($29)
+	jr	$31
+# Function write_1darr
+write_1darr:
+	sw	$31, -4($29)
+	sw	$20, -24($29)
+	sw	$19, -20($29)
+	sw	$18, -16($29)
+	sw	$17, -12($29)
+	sw	$16, -8($29)
+	addi	$29, $29, -28
+# 	ori	_param_x_4_,$2,0
+# 	ori	_arr_reg_7_,_param_x_4_,0
+	lw	$16, 0($2)
+# was:	lw	_size_reg_6_, 0(_arr_reg_7_)
+	ori	$17, $28, 0
+# was:	ori	_write_1darrres_5_, $28, 0
+	sll	$3, $16, 2
+# was:	sll	_tmp_16_, _size_reg_6_, 2
+	addi	$3, $3, 4
+# was:	addi	_tmp_16_, _tmp_16_, 4
+	add	$28, $28, $3
+# was:	add	$28, $28, _tmp_16_
+	sw	$16, 0($17)
+# was:	sw	_size_reg_6_, 0(_write_1darrres_5_)
+	addi	$18, $17, 4
+# was:	addi	_addr_reg_10_, _write_1darrres_5_, 4
+	ori	$19, $0, 0
+# was:	ori	_i_reg_11_, $0, 0
+	addi	$20, $2, 4
+# was:	addi	_elem_reg_8_, _arr_reg_7_, 4
+_loop_beg_12_:
+	sub	$2, $19, $16
+# was:	sub	_tmp_reg_14_, _i_reg_11_, _size_reg_6_
+	bgez	$2, _loop_end_13_
+# was:	bgez	_tmp_reg_14_, _loop_end_13_
+	lw	$2, 0($20)
+# was:	lw	_res_reg_9_, 0(_elem_reg_8_)
+	addi	$20, $20, 4
+# was:	addi	_elem_reg_8_, _elem_reg_8_, 4
+# 	ori	$2,_res_reg_9_,0
+	jal	write_int
+# was:	jal	write_int, $2
+# 	ori	_tmp_reg_15_,$2,0
+# 	ori	_res_reg_9_,_tmp_reg_15_,0
+	sw	$2, 0($18)
+# was:	sw	_res_reg_9_, 0(_addr_reg_10_)
+	addi	$18, $18, 4
+# was:	addi	_addr_reg_10_, _addr_reg_10_, 4
+	addi	$19, $19, 1
+# was:	addi	_i_reg_11_, _i_reg_11_, 1
+	j	_loop_beg_12_
+_loop_end_13_:
+	ori	$2, $17, 0
+# was:	ori	$2, _write_1darrres_5_, 0
+	addi	$29, $29, 28
+	lw	$20, -24($29)
+	lw	$19, -20($29)
+	lw	$18, -16($29)
+	lw	$17, -12($29)
+	lw	$16, -8($29)
+	lw	$31, -4($29)
+	jr	$31
+# Function write_2darr
+write_2darr:
+	sw	$31, -4($29)
+	sw	$20, -24($29)
+	sw	$19, -20($29)
+	sw	$18, -16($29)
+	sw	$17, -12($29)
+	sw	$16, -8($29)
+	addi	$29, $29, -28
+# 	ori	_param_x_17_,$2,0
+# 	ori	_arr_reg_20_,_param_x_17_,0
+	lw	$16, 0($2)
+# was:	lw	_size_reg_19_, 0(_arr_reg_20_)
+	ori	$17, $28, 0
+# was:	ori	_write_2darrres_18_, $28, 0
+	sll	$3, $16, 2
+# was:	sll	_tmp_29_, _size_reg_19_, 2
+	addi	$3, $3, 4
+# was:	addi	_tmp_29_, _tmp_29_, 4
+	add	$28, $28, $3
+# was:	add	$28, $28, _tmp_29_
+	sw	$16, 0($17)
+# was:	sw	_size_reg_19_, 0(_write_2darrres_18_)
+	addi	$18, $17, 4
+# was:	addi	_addr_reg_23_, _write_2darrres_18_, 4
+	ori	$19, $0, 0
+# was:	ori	_i_reg_24_, $0, 0
+	addi	$20, $2, 4
+# was:	addi	_elem_reg_21_, _arr_reg_20_, 4
+_loop_beg_25_:
+	sub	$2, $19, $16
+# was:	sub	_tmp_reg_27_, _i_reg_24_, _size_reg_19_
+	bgez	$2, _loop_end_26_
+# was:	bgez	_tmp_reg_27_, _loop_end_26_
+	lw	$2, 0($20)
+# was:	lw	_res_reg_22_, 0(_elem_reg_21_)
+	addi	$20, $20, 4
+# was:	addi	_elem_reg_21_, _elem_reg_21_, 4
+# 	ori	$2,_res_reg_22_,0
+	jal	write_1darr
+# was:	jal	write_1darr, $2
+# 	ori	_tmp_reg_28_,$2,0
+# 	ori	_res_reg_22_,_tmp_reg_28_,0
+	sw	$2, 0($18)
+# was:	sw	_res_reg_22_, 0(_addr_reg_23_)
+	addi	$18, $18, 4
+# was:	addi	_addr_reg_23_, _addr_reg_23_, 4
+	addi	$19, $19, 1
+# was:	addi	_i_reg_24_, _i_reg_24_, 1
+	j	_loop_beg_25_
+_loop_end_26_:
+	ori	$2, $17, 0
+# was:	ori	$2, _write_2darrres_18_, 0
+	addi	$29, $29, 28
+	lw	$20, -24($29)
+	lw	$19, -20($29)
+	lw	$18, -16($29)
+	lw	$17, -12($29)
+	lw	$16, -8($29)
+	lw	$31, -4($29)
+	jr	$31
+# Function even
+even:
+	sw	$31, -4($29)
+	addi	$29, $29, -8
+# 	ori	_param_a_30_,$2,0
+# 	ori	_divide_L_36_,_param_a_30_,0
+	ori	$3, $0, 2
+# was:	ori	_divide_R_37_, $0, 2
+	div	$4, $2, $3
+# was:	div	_times_L_34_, _divide_L_36_, _divide_R_37_
+	ori	$3, $0, 2
+# was:	ori	_times_R_35_, $0, 2
+	mul	$3, $4, $3
+# was:	mul	_eq_L_32_, _times_L_34_, _times_R_35_
+# 	ori	_eq_R_33_,_param_a_30_,0
+	ori	$4, $0, 0
+# was:	ori	_evenres_31_, $0, 0
+	bne	$3, $2, _false_38_
+# was:	bne	_eq_L_32_, _eq_R_33_, _false_38_
+	ori	$4, $0, 1
+# was:	ori	_evenres_31_, $0, 1
+_false_38_:
+	ori	$2, $4, 0
+# was:	ori	$2, _evenres_31_, 0
+	addi	$29, $29, 8
+	lw	$31, -4($29)
+	jr	$31
 # Function main
 main:
 	sw	$31, -4($29)
-	sw	$25, -48($29)
-	sw	$24, -44($29)
-	sw	$23, -40($29)
-	sw	$22, -36($29)
-	sw	$21, -32($29)
-	sw	$20, -28($29)
-	sw	$19, -24($29)
-	sw	$18, -20($29)
-	sw	$17, -16($29)
-	sw	$16, -12($29)
-	addi	$29, $29, -52
-	sw	$2, 0($29)
-# was:	sw	_fun_arg_res_84_, 0($29)
+	sw	$22, -32($29)
+	sw	$21, -28($29)
+	sw	$20, -24($29)
+	sw	$19, -20($29)
+	sw	$18, -16($29)
+	sw	$17, -12($29)
+	sw	$16, -8($29)
+	addi	$29, $29, -36
 	jal	getint
 # was:	jal	getint, $2
-# 	ori	_letBind_2_,$2,0
+# 	ori	_letBind_40_,$2,0
 	ori	$3, $2, 0
-# was:	ori	_size_reg_8_, _letBind_2_, 0
-	bgez	$3, _safe_lab_9_
-# was:	bgez	_size_reg_8_, _safe_lab_9_
+# was:	ori	_size_reg_46_, _letBind_40_, 0
+	bgez	$3, _safe_lab_47_
+# was:	bgez	_size_reg_46_, _safe_lab_47_
 	ori	$5, $0, 11
 # was:	ori	$5, $0, 11
 	la	$6, _Msg_IllegalArraySize_
 # was:	la	$6, _Msg_IllegalArraySize_
 	j	_RuntimeError_
-_safe_lab_9_:
+_safe_lab_47_:
 	ori	$2, $28, 0
-# was:	ori	_arr_reg_5_, $28, 0
+# was:	ori	_arr_reg_43_, $28, 0
 	sll	$4, $3, 2
-# was:	sll	_tmp_15_, _size_reg_8_, 2
+# was:	sll	_tmp_53_, _size_reg_46_, 2
 	addi	$4, $4, 4
-# was:	addi	_tmp_15_, _tmp_15_, 4
+# was:	addi	_tmp_53_, _tmp_53_, 4
 	add	$28, $28, $4
-# was:	add	$28, $28, _tmp_15_
+# was:	add	$28, $28, _tmp_53_
 	sw	$3, 0($2)
-# was:	sw	_size_reg_8_, 0(_arr_reg_5_)
-	addi	$4, $2, 4
-# was:	addi	_addr_reg_10_, _arr_reg_5_, 4
-	ori	$5, $0, 0
-# was:	ori	_i_reg_11_, $0, 0
-_loop_beg_12_:
-	sub	$6, $5, $3
-# was:	sub	_tmp_reg_14_, _i_reg_11_, _size_reg_8_
-	bgez	$6, _loop_end_13_
-# was:	bgez	_tmp_reg_14_, _loop_end_13_
-	sw	$5, 0($4)
-# was:	sw	_i_reg_11_, 0(_addr_reg_10_)
-	addi	$4, $4, 4
-# was:	addi	_addr_reg_10_, _addr_reg_10_, 4
-	addi	$5, $5, 1
-# was:	addi	_i_reg_11_, _i_reg_11_, 1
-	j	_loop_beg_12_
-_loop_end_13_:
-	lw	$5, 0($2)
-# was:	lw	_size_reg_4_, 0(_arr_reg_5_)
+# was:	sw	_size_reg_46_, 0(_arr_reg_43_)
+	addi	$6, $2, 4
+# was:	addi	_addr_reg_48_, _arr_reg_43_, 4
+	ori	$4, $0, 0
+# was:	ori	_i_reg_49_, $0, 0
+_loop_beg_50_:
+	sub	$5, $4, $3
+# was:	sub	_tmp_reg_52_, _i_reg_49_, _size_reg_46_
+	bgez	$5, _loop_end_51_
+# was:	bgez	_tmp_reg_52_, _loop_end_51_
+	sw	$4, 0($6)
+# was:	sw	_i_reg_49_, 0(_addr_reg_48_)
+	addi	$6, $6, 4
+# was:	addi	_addr_reg_48_, _addr_reg_48_, 4
+	addi	$4, $4, 1
+# was:	addi	_i_reg_49_, _i_reg_49_, 1
+	j	_loop_beg_50_
+_loop_end_51_:
+	lw	$3, 0($2)
+# was:	lw	_size_reg_42_, 0(_arr_reg_43_)
 	ori	$4, $28, 0
-# was:	ori	_letBind_3_, $28, 0
-	sll	$3, $5, 2
-# was:	sll	_tmp_32_, _size_reg_4_, 2
-	addi	$3, $3, 4
-# was:	addi	_tmp_32_, _tmp_32_, 4
-	add	$28, $28, $3
-# was:	add	$28, $28, _tmp_32_
-	sw	$5, 0($4)
-# was:	sw	_size_reg_4_, 0(_letBind_3_)
+# was:	ori	_letBind_41_, $28, 0
+	sll	$5, $3, 2
+# was:	sll	_tmp_70_, _size_reg_42_, 2
+	addi	$5, $5, 4
+# was:	addi	_tmp_70_, _tmp_70_, 4
+	add	$28, $28, $5
+# was:	add	$28, $28, _tmp_70_
+	sw	$3, 0($4)
+# was:	sw	_size_reg_42_, 0(_letBind_41_)
 	addi	$6, $4, 4
-# was:	addi	_addr_reg_16_, _letBind_3_, 4
-	ori	$7, $0, 0
-# was:	ori	_i_reg_17_, $0, 0
-	addi	$3, $2, 4
-# was:	addi	_elem_reg_6_, _arr_reg_5_, 4
-_loop_beg_18_:
-	sub	$2, $7, $5
-# was:	sub	_tmp_reg_20_, _i_reg_17_, _size_reg_4_
-	bgez	$2, _loop_end_19_
-# was:	bgez	_tmp_reg_20_, _loop_end_19_
-	lw	$8, 0($3)
-# was:	lw	_res_reg_7_, 0(_elem_reg_6_)
-	addi	$3, $3, 4
-# was:	addi	_elem_reg_6_, _elem_reg_6_, 4
-# 	ori	_plus_L_23_,_res_reg_7_,0
+# was:	addi	_addr_reg_54_, _letBind_41_, 4
+	ori	$5, $0, 0
+# was:	ori	_i_reg_55_, $0, 0
+	addi	$7, $2, 4
+# was:	addi	_elem_reg_44_, _arr_reg_43_, 4
+_loop_beg_56_:
+	sub	$2, $5, $3
+# was:	sub	_tmp_reg_58_, _i_reg_55_, _size_reg_42_
+	bgez	$2, _loop_end_57_
+# was:	bgez	_tmp_reg_58_, _loop_end_57_
+	lw	$2, 0($7)
+# was:	lw	_res_reg_45_, 0(_elem_reg_44_)
+	addi	$7, $7, 4
+# was:	addi	_elem_reg_44_, _elem_reg_44_, 4
+	ori	$8, $2, 0
+# was:	ori	_plus_L_61_, _res_reg_45_, 0
 	ori	$2, $0, 2
-# was:	ori	_plus_R_24_, $0, 2
-	add	$2, $8, $2
-# was:	add	_size_reg_22_, _plus_L_23_, _plus_R_24_
-	bgez	$2, _safe_lab_25_
-# was:	bgez	_size_reg_22_, _safe_lab_25_
+# was:	ori	_plus_R_62_, $0, 2
+	add	$8, $8, $2
+# was:	add	_size_reg_60_, _plus_L_61_, _plus_R_62_
+	bgez	$8, _safe_lab_63_
+# was:	bgez	_size_reg_60_, _safe_lab_63_
 	ori	$5, $0, 10
 # was:	ori	$5, $0, 10
 	la	$6, _Msg_IllegalArraySize_
 # was:	la	$6, _Msg_IllegalArraySize_
 	j	_RuntimeError_
-_safe_lab_25_:
-	ori	$8, $28, 0
-# was:	ori	_fun_arg_res_21_, $28, 0
-	sll	$9, $2, 2
-# was:	sll	_tmp_31_, _size_reg_22_, 2
+_safe_lab_63_:
+	ori	$2, $28, 0
+# was:	ori	_fun_arg_res_59_, $28, 0
+	sll	$9, $8, 2
+# was:	sll	_tmp_69_, _size_reg_60_, 2
 	addi	$9, $9, 4
-# was:	addi	_tmp_31_, _tmp_31_, 4
+# was:	addi	_tmp_69_, _tmp_69_, 4
 	add	$28, $28, $9
-# was:	add	$28, $28, _tmp_31_
-	sw	$2, 0($8)
-# was:	sw	_size_reg_22_, 0(_fun_arg_res_21_)
-	addi	$10, $8, 4
-# was:	addi	_addr_reg_26_, _fun_arg_res_21_, 4
-	ori	$9, $0, 0
-# was:	ori	_i_reg_27_, $0, 0
-_loop_beg_28_:
-	sub	$11, $9, $2
-# was:	sub	_tmp_reg_30_, _i_reg_27_, _size_reg_22_
-	bgez	$11, _loop_end_29_
-# was:	bgez	_tmp_reg_30_, _loop_end_29_
-	sw	$9, 0($10)
-# was:	sw	_i_reg_27_, 0(_addr_reg_26_)
+# was:	add	$28, $28, _tmp_69_
+	sw	$8, 0($2)
+# was:	sw	_size_reg_60_, 0(_fun_arg_res_59_)
+	addi	$10, $2, 4
+# was:	addi	_addr_reg_64_, _fun_arg_res_59_, 4
+	ori	$11, $0, 0
+# was:	ori	_i_reg_65_, $0, 0
+_loop_beg_66_:
+	sub	$9, $11, $8
+# was:	sub	_tmp_reg_68_, _i_reg_65_, _size_reg_60_
+	bgez	$9, _loop_end_67_
+# was:	bgez	_tmp_reg_68_, _loop_end_67_
+	sw	$11, 0($10)
+# was:	sw	_i_reg_65_, 0(_addr_reg_64_)
 	addi	$10, $10, 4
-# was:	addi	_addr_reg_26_, _addr_reg_26_, 4
-	addi	$9, $9, 1
-# was:	addi	_i_reg_27_, _i_reg_27_, 1
-	j	_loop_beg_28_
-_loop_end_29_:
-# 	ori	_res_reg_7_,_fun_arg_res_21_,0
-	sw	$8, 0($6)
-# was:	sw	_res_reg_7_, 0(_addr_reg_16_)
+# was:	addi	_addr_reg_64_, _addr_reg_64_, 4
+	addi	$11, $11, 1
+# was:	addi	_i_reg_65_, _i_reg_65_, 1
+	j	_loop_beg_66_
+_loop_end_67_:
+# 	ori	_res_reg_45_,_fun_arg_res_59_,0
+	sw	$2, 0($6)
+# was:	sw	_res_reg_45_, 0(_addr_reg_54_)
 	addi	$6, $6, 4
-# was:	addi	_addr_reg_16_, _addr_reg_16_, 4
-	addi	$7, $7, 1
-# was:	addi	_i_reg_17_, _i_reg_17_, 1
-	j	_loop_beg_18_
-_loop_end_19_:
-	ori	$3, $4, 0
-# was:	ori	_arr_reg_35_, _letBind_3_, 0
-	lw	$2, 0($3)
-# was:	lw	_size_reg_34_, 0(_arr_reg_35_)
-	ori	$4, $28, 0
-# was:	ori	_letBind_33_, $28, 0
-	sll	$5, $2, 2
-# was:	sll	_tmp_64_, _size_reg_34_, 2
-	addi	$5, $5, 4
-# was:	addi	_tmp_64_, _tmp_64_, 4
-	add	$28, $28, $5
-# was:	add	$28, $28, _tmp_64_
-	sw	$2, 0($4)
-# was:	sw	_size_reg_34_, 0(_letBind_33_)
-	addi	$6, $4, 4
-# was:	addi	_addr_reg_39_, _letBind_33_, 4
-	addi	$3, $3, 4
-# was:	addi	_arr_reg_35_, _arr_reg_35_, 4
-	ori	$5, $0, 0
-# was:	ori	_i_reg_40_, $0, 0
-	ori	$7, $0, 0
-# was:	ori	_count_reg_38_, $0, 0
-_loop_beg_41_:
-	sub	$8, $5, $2
-# was:	sub	_tmp_reg_44_, _i_reg_40_, _size_reg_34_
-	bgez	$8, _loop_end_42_
-# was:	bgez	_tmp_reg_44_, _loop_end_42_
-	lw	$8, 0($3)
-# was:	lw	_elem_reg_36_, 0(_arr_reg_35_)
-	addi	$3, $3, 4
-# was:	addi	_arr_reg_35_, _arr_reg_35_, 4
-	ori	$10, $8, 0
-# was:	ori	_arr_reg_47_, _elem_reg_36_, 0
-	lw	$11, 0($10)
-# was:	lw	_size_reg_48_, 0(_arr_reg_47_)
-	ori	$13, $0, 0
-# was:	ori	_letBind_46_, $0, 0
-	addi	$10, $10, 4
-# was:	addi	_arr_reg_47_, _arr_reg_47_, 4
-	ori	$9, $0, 0
-# was:	ori	_ind_var_49_, $0, 0
-_loop_beg_51_:
-	sub	$12, $9, $11
-# was:	sub	_tmp_reg_50_, _ind_var_49_, _size_reg_48_
-	bgez	$12, _loop_end_52_
-# was:	bgez	_tmp_reg_50_, _loop_end_52_
-	lw	$12, 0($10)
-# was:	lw	_tmp_reg_50_, 0(_arr_reg_47_)
-	addi	$10, $10, 4
-# was:	addi	_arr_reg_47_, _arr_reg_47_, 4
-# 	ori	_plus_L_54_,_letBind_46_,0
-# 	ori	_plus_R_55_,_tmp_reg_50_,0
-	add	$13, $13, $12
-# was:	add	_fun_arg_res_53_, _plus_L_54_, _plus_R_55_
-# 	ori	_letBind_46_,_fun_arg_res_53_,0
-	addi	$9, $9, 1
-# was:	addi	_ind_var_49_, _ind_var_49_, 1
-	j	_loop_beg_51_
-_loop_end_52_:
-# 	ori	_div1_L_60_,_letBind_46_,0
-	ori	$9, $0, 2
-# was:	ori	_div2_R_61_, $0, 2
-	bne	$9, $0, _safe_div_62_
-# was:	bne	_div2_R_61_, $0, _safe_div_62_
-	ori	$5, $0, 6
-# was:	ori	$5, $0, 6
-	la	$6, _Msg_DivZero_
-# was:	la	$6, _Msg_DivZero_
-	j	_RuntimeError_
-_safe_div_62_:
-	div	$10, $13, $9
-# was:	div	_mult1_L_58_, _div1_L_60_, _div2_R_61_
-	ori	$9, $0, 2
-# was:	ori	_mult2_R_59_, $0, 2
-	mul	$9, $10, $9
-# was:	mul	_eq_L_56_, _mult1_L_58_, _mult2_R_59_
-# 	ori	_eq_R_57_,_letBind_46_,0
-	ori	$10, $0, 0
-# was:	ori	_fun_arg_res_45_, $0, 0
-	bne	$9, $13, _false_63_
-# was:	bne	_eq_L_56_, _eq_R_57_, _false_63_
-	ori	$10, $0, 1
-# was:	ori	_fun_arg_res_45_, $0, 1
-_false_63_:
-# 	ori	_bool_reg_37_,_fun_arg_res_45_,0
-	beq	$10, $0, _if_end_43_
-# was:	beq	_bool_reg_37_, $0, _if_end_43_
-	sw	$8, 0($6)
-# was:	sw	_elem_reg_36_, 0(_addr_reg_39_)
-	addi	$6, $6, 4
-# was:	addi	_addr_reg_39_, _addr_reg_39_, 4
-	addi	$7, $7, 1
-# was:	addi	_count_reg_38_, _count_reg_38_, 1
-_if_end_43_:
+# was:	addi	_addr_reg_54_, _addr_reg_54_, 4
 	addi	$5, $5, 1
-# was:	addi	_i_reg_40_, _i_reg_40_, 1
-	j	_loop_beg_41_
-_loop_end_42_:
-	sw	$7, 0($4)
-# was:	sw	_count_reg_38_, 0(_letBind_33_)
-# 	ori	_arr_reg_66_,_letBind_33_,0
+# was:	addi	_i_reg_55_, _i_reg_55_, 1
+	j	_loop_beg_56_
+_loop_end_57_:
+# 	ori	_arr_reg_73_,_letBind_41_,0
 	lw	$17, 0($4)
-# was:	lw	_size_reg_65_, 0(_arr_reg_66_)
+# was:	lw	_size_reg_72_, 0(_arr_reg_73_)
 	ori	$16, $28, 0
-# was:	ori	_mainres_1_, $28, 0
+# was:	ori	_letBind_71_, $28, 0
 	sll	$2, $17, 2
-# was:	sll	_tmp_87_, _size_reg_65_, 2
+# was:	sll	_tmp_96_, _size_reg_72_, 2
 	addi	$2, $2, 4
-# was:	addi	_tmp_87_, _tmp_87_, 4
+# was:	addi	_tmp_96_, _tmp_96_, 4
 	add	$28, $28, $2
-# was:	add	$28, $28, _tmp_87_
+# was:	add	$28, $28, _tmp_96_
 	sw	$17, 0($16)
-# was:	sw	_size_reg_65_, 0(_mainres_1_)
+# was:	sw	_size_reg_72_, 0(_letBind_71_)
 	addi	$19, $16, 4
-# was:	addi	_addr_reg_69_, _mainres_1_, 4
+# was:	addi	_addr_reg_77_, _letBind_71_, 4
+	ori	$20, $0, 0
+# was:	ori	_i_reg_78_, $0, 0
 	ori	$18, $0, 0
-# was:	ori	_i_reg_70_, $0, 0
-	addi	$20, $4, 4
-# was:	addi	_elem_reg_67_, _arr_reg_66_, 4
-_loop_beg_71_:
-	sub	$2, $18, $17
-# was:	sub	_tmp_reg_73_, _i_reg_70_, _size_reg_65_
-	bgez	$2, _loop_end_72_
-# was:	bgez	_tmp_reg_73_, _loop_end_72_
-	lw	$2, 0($20)
-# was:	lw	_res_reg_68_, 0(_elem_reg_67_)
-	addi	$20, $20, 4
-# was:	addi	_elem_reg_67_, _elem_reg_67_, 4
-# 	ori	_arr_reg_76_,_res_reg_68_,0
-	lw	$22, 0($2)
-# was:	lw	_size_reg_75_, 0(_arr_reg_76_)
-	ori	$21, $28, 0
-# was:	ori	_fun_arg_res_74_, $28, 0
-	sll	$3, $22, 2
-# was:	sll	_tmp_86_, _size_reg_75_, 2
+# was:	ori	_j_reg_79_, $0, 0
+	addi	$21, $4, 4
+# was:	addi	_elem_reg_74_, _arr_reg_73_, 4
+_loop_beg_80_:
+	sub	$2, $20, $17
+# was:	sub	_tmp_reg_83_, _i_reg_78_, _size_reg_72_
+	bgez	$2, _loop_end_81_
+# was:	bgez	_tmp_reg_83_, _loop_end_81_
+	lw	$22, 0($21)
+# was:	lw	_res_reg_75_, 0(_elem_reg_74_)
+	addi	$21, $21, 4
+# was:	addi	_elem_reg_74_, _elem_reg_74_, 4
+	ori	$3, $22, 0
+# was:	ori	_arr_reg_86_, _res_reg_75_, 0
+	lw	$2, 0($3)
+# was:	lw	_size_reg_87_, 0(_arr_reg_86_)
+	ori	$6, $0, 0
+# was:	ori	_letBind_85_, $0, 0
 	addi	$3, $3, 4
-# was:	addi	_tmp_86_, _tmp_86_, 4
-	add	$28, $28, $3
-# was:	add	$28, $28, _tmp_86_
-	sw	$22, 0($21)
-# was:	sw	_size_reg_75_, 0(_fun_arg_res_74_)
-	addi	$23, $21, 4
-# was:	addi	_addr_reg_79_, _fun_arg_res_74_, 4
-	ori	$24, $0, 0
-# was:	ori	_i_reg_80_, $0, 0
-	addi	$25, $2, 4
-# was:	addi	_elem_reg_77_, _arr_reg_76_, 4
-_loop_beg_81_:
-	sub	$2, $24, $22
-# was:	sub	_tmp_reg_83_, _i_reg_80_, _size_reg_75_
-	bgez	$2, _loop_end_82_
-# was:	bgez	_tmp_reg_83_, _loop_end_82_
-	lw	$2, 0($25)
-# was:	lw	_res_reg_78_, 0(_elem_reg_77_)
-	addi	$25, $25, 4
-# was:	addi	_elem_reg_77_, _elem_reg_77_, 4
-# 	ori	_tmp_85_,_res_reg_78_,0
-# 	ori	_fun_arg_res_84_,_tmp_85_,0
-	sw	$2, 0($29)
-# was:	sw	_fun_arg_res_84_, 0($29)
-	lw	$2, 0($29)
-# was:	lw	_fun_arg_res_84_, 0($29)
-# 	ori	$2,_fun_arg_res_84_,0
-	jal	putint
-# was:	jal	putint, $2
-	lw	$2, 0($29)
-# was:	lw	_fun_arg_res_84_, 0($29)
-# 	ori	_res_reg_78_,_fun_arg_res_84_,0
-	sw	$2, 0($23)
-# was:	sw	_res_reg_78_, 0(_addr_reg_79_)
-	addi	$23, $23, 4
-# was:	addi	_addr_reg_79_, _addr_reg_79_, 4
-	addi	$24, $24, 1
-# was:	addi	_i_reg_80_, _i_reg_80_, 1
-	j	_loop_beg_81_
-_loop_end_82_:
-	ori	$2, $21, 0
-# was:	ori	_res_reg_68_, _fun_arg_res_74_, 0
-	sw	$2, 0($19)
-# was:	sw	_res_reg_68_, 0(_addr_reg_69_)
-	addi	$19, $19, 4
-# was:	addi	_addr_reg_69_, _addr_reg_69_, 4
+# was:	addi	_arr_reg_86_, _arr_reg_86_, 4
+	ori	$4, $0, 0
+# was:	ori	_ind_var_88_, $0, 0
+_loop_beg_90_:
+	sub	$5, $4, $2
+# was:	sub	_tmp_reg_89_, _ind_var_88_, _size_reg_87_
+	bgez	$5, _loop_end_91_
+# was:	bgez	_tmp_reg_89_, _loop_end_91_
+	lw	$5, 0($3)
+# was:	lw	_tmp_reg_89_, 0(_arr_reg_86_)
+	addi	$3, $3, 4
+# was:	addi	_arr_reg_86_, _arr_reg_86_, 4
+# 	ori	_plus_L_93_,_letBind_85_,0
+# 	ori	_plus_R_94_,_tmp_reg_89_,0
+	add	$6, $6, $5
+# was:	add	_fun_arg_res_92_, _plus_L_93_, _plus_R_94_
+# 	ori	_letBind_85_,_fun_arg_res_92_,0
+	addi	$4, $4, 1
+# was:	addi	_ind_var_88_, _ind_var_88_, 1
+	j	_loop_beg_90_
+_loop_end_91_:
+	ori	$2, $6, 0
+# was:	ori	_arg_95_, _letBind_85_, 0
+# 	ori	$2,_arg_95_,0
+	jal	even
+# was:	jal	even, $2
+# 	ori	_fun_arg_res_84_,$2,0
+# 	ori	_bool_reg_76_,_fun_arg_res_84_,0
+	beq	$2, $0, _not_true_82_
+# was:	beq	_bool_reg_76_, $0, _not_true_82_
+	sw	$22, 0($19)
+# was:	sw	_res_reg_75_, 0(_addr_reg_77_)
 	addi	$18, $18, 1
-# was:	addi	_i_reg_70_, _i_reg_70_, 1
-	j	_loop_beg_71_
-_loop_end_72_:
+# was:	addi	_j_reg_79_, _j_reg_79_, 1
+	addi	$19, $19, 4
+# was:	addi	_addr_reg_77_, _addr_reg_77_, 4
+_not_true_82_:
+	addi	$20, $20, 1
+# was:	addi	_i_reg_78_, _i_reg_78_, 1
+	j	_loop_beg_80_
+_loop_end_81_:
+	sw	$18, 0($16)
+# was:	sw	_j_reg_79_, 0(_letBind_71_)
 	ori	$2, $16, 0
-# was:	ori	$2, _mainres_1_, 0
-	addi	$29, $29, 52
-	lw	$25, -48($29)
-	lw	$24, -44($29)
-	lw	$23, -40($29)
-	lw	$22, -36($29)
-	lw	$21, -32($29)
-	lw	$20, -28($29)
-	lw	$19, -24($29)
-	lw	$18, -20($29)
-	lw	$17, -16($29)
-	lw	$16, -12($29)
+# was:	ori	_arg_97_, _letBind_71_, 0
+# 	ori	$2,_arg_97_,0
+	jal	write_2darr
+# was:	jal	write_2darr, $2
+# 	ori	_mainres_39_,$2,0
+# 	ori	$2,_mainres_39_,0
+	addi	$29, $29, 36
+	lw	$22, -32($29)
+	lw	$21, -28($29)
+	lw	$20, -24($29)
+	lw	$19, -20($29)
+	lw	$18, -16($29)
+	lw	$17, -12($29)
+	lw	$16, -8($29)
 	lw	$31, -4($29)
 	jr	$31
 ord:
diff --git a/tests/filter.asm b/tests/filter.asm
index a823eea..670ee85 100644
--- a/tests/filter.asm
+++ b/tests/filter.asm
@@ -17,288 +17,328 @@
 _stop_:
 	ori	$2, $0, 10
 	syscall
+# Function write_int
+write_int:
+	sw	$31, -4($29)
+	sw	$16, -8($29)
+	addi	$29, $29, -12
+# 	ori	_param_x_1_,$2,0
+	ori	$16, $2, 0
+# was:	ori	_tmp_3_, _param_x_1_, 0
+# 	ori	_write_intres_2_,_tmp_3_,0
+	ori	$2, $16, 0
+# was:	ori	$2, _write_intres_2_, 0
+	jal	putint
+# was:	jal	putint, $2
+	ori	$2, $16, 0
+# was:	ori	$2, _write_intres_2_, 0
+	addi	$29, $29, 12
+	lw	$16, -8($29)
+	lw	$31, -4($29)
+	jr	$31
+# Function write_int_arr
+write_int_arr:
+	sw	$31, -4($29)
+	sw	$20, -24($29)
+	sw	$19, -20($29)
+	sw	$18, -16($29)
+	sw	$17, -12($29)
+	sw	$16, -8($29)
+	addi	$29, $29, -28
+# 	ori	_param_x_4_,$2,0
+# 	ori	_arr_reg_7_,_param_x_4_,0
+	lw	$16, 0($2)
+# was:	lw	_size_reg_6_, 0(_arr_reg_7_)
+	ori	$17, $28, 0
+# was:	ori	_write_int_arrres_5_, $28, 0
+	sll	$3, $16, 2
+# was:	sll	_tmp_16_, _size_reg_6_, 2
+	addi	$3, $3, 4
+# was:	addi	_tmp_16_, _tmp_16_, 4
+	add	$28, $28, $3
+# was:	add	$28, $28, _tmp_16_
+	sw	$16, 0($17)
+# was:	sw	_size_reg_6_, 0(_write_int_arrres_5_)
+	addi	$18, $17, 4
+# was:	addi	_addr_reg_10_, _write_int_arrres_5_, 4
+	ori	$19, $0, 0
+# was:	ori	_i_reg_11_, $0, 0
+	addi	$20, $2, 4
+# was:	addi	_elem_reg_8_, _arr_reg_7_, 4
+_loop_beg_12_:
+	sub	$2, $19, $16
+# was:	sub	_tmp_reg_14_, _i_reg_11_, _size_reg_6_
+	bgez	$2, _loop_end_13_
+# was:	bgez	_tmp_reg_14_, _loop_end_13_
+	lw	$2, 0($20)
+# was:	lw	_res_reg_9_, 0(_elem_reg_8_)
+	addi	$20, $20, 4
+# was:	addi	_elem_reg_8_, _elem_reg_8_, 4
+# 	ori	$2,_res_reg_9_,0
+	jal	write_int
+# was:	jal	write_int, $2
+# 	ori	_tmp_reg_15_,$2,0
+# 	ori	_res_reg_9_,_tmp_reg_15_,0
+	sw	$2, 0($18)
+# was:	sw	_res_reg_9_, 0(_addr_reg_10_)
+	addi	$18, $18, 4
+# was:	addi	_addr_reg_10_, _addr_reg_10_, 4
+	addi	$19, $19, 1
+# was:	addi	_i_reg_11_, _i_reg_11_, 1
+	j	_loop_beg_12_
+_loop_end_13_:
+	ori	$2, $17, 0
+# was:	ori	$2, _write_int_arrres_5_, 0
+	addi	$29, $29, 28
+	lw	$20, -24($29)
+	lw	$19, -20($29)
+	lw	$18, -16($29)
+	lw	$17, -12($29)
+	lw	$16, -8($29)
+	lw	$31, -4($29)
+	jr	$31
+# Function isMul16
+isMul16:
+	sw	$31, -4($29)
+	addi	$29, $29, -8
+# 	ori	_param_a_17_,$2,0
+# 	ori	_divide_L_23_,_param_a_17_,0
+	ori	$3, $0, 16
+# was:	ori	_divide_R_24_, $0, 16
+	div	$4, $2, $3
+# was:	div	_times_L_21_, _divide_L_23_, _divide_R_24_
+	ori	$3, $0, 16
+# was:	ori	_times_R_22_, $0, 16
+	mul	$3, $4, $3
+# was:	mul	_eq_L_19_, _times_L_21_, _times_R_22_
+# 	ori	_eq_R_20_,_param_a_17_,0
+	ori	$4, $0, 0
+# was:	ori	_isMul16res_18_, $0, 0
+	bne	$3, $2, _false_25_
+# was:	bne	_eq_L_19_, _eq_R_20_, _false_25_
+	ori	$4, $0, 1
+# was:	ori	_isMul16res_18_, $0, 1
+_false_25_:
+	ori	$2, $4, 0
+# was:	ori	$2, _isMul16res_18_, 0
+	addi	$29, $29, 8
+	lw	$31, -4($29)
+	jr	$31
 # Function main
 main:
 	sw	$31, -4($29)
+	sw	$22, -32($29)
 	sw	$21, -28($29)
 	sw	$20, -24($29)
 	sw	$19, -20($29)
 	sw	$18, -16($29)
 	sw	$17, -12($29)
 	sw	$16, -8($29)
-	addi	$29, $29, -32
+	addi	$29, $29, -36
 	jal	getint
 # was:	jal	getint, $2
-# 	ori	_letBind_2_,$2,0
-	ori	$3, $2, 0
-# was:	ori	_size_reg_9_, _letBind_2_, 0
-	bgez	$3, _safe_lab_10_
-# was:	bgez	_size_reg_9_, _safe_lab_10_
+# 	ori	_letBind_27_,$2,0
+# 	ori	_size_reg_34_,_letBind_27_,0
+	bgez	$2, _safe_lab_35_
+# was:	bgez	_size_reg_34_, _safe_lab_35_
 	ori	$5, $0, 10
 # was:	ori	$5, $0, 10
 	la	$6, _Msg_IllegalArraySize_
 # was:	la	$6, _Msg_IllegalArraySize_
 	j	_RuntimeError_
-_safe_lab_10_:
-	ori	$2, $28, 0
-# was:	ori	_arr_reg_5_, $28, 0
-	sll	$4, $3, 2
-# was:	sll	_tmp_16_, _size_reg_9_, 2
-	addi	$4, $4, 4
-# was:	addi	_tmp_16_, _tmp_16_, 4
-	add	$28, $28, $4
-# was:	add	$28, $28, _tmp_16_
-	sw	$3, 0($2)
-# was:	sw	_size_reg_9_, 0(_arr_reg_5_)
-	addi	$5, $2, 4
-# was:	addi	_addr_reg_11_, _arr_reg_5_, 4
-	ori	$6, $0, 0
-# was:	ori	_i_reg_12_, $0, 0
-_loop_beg_13_:
-	sub	$4, $6, $3
-# was:	sub	_tmp_reg_15_, _i_reg_12_, _size_reg_9_
-	bgez	$4, _loop_end_14_
-# was:	bgez	_tmp_reg_15_, _loop_end_14_
-	sw	$6, 0($5)
-# was:	sw	_i_reg_12_, 0(_addr_reg_11_)
-	addi	$5, $5, 4
-# was:	addi	_addr_reg_11_, _addr_reg_11_, 4
-	addi	$6, $6, 1
-# was:	addi	_i_reg_12_, _i_reg_12_, 1
-	j	_loop_beg_13_
-_loop_end_14_:
-	lw	$5, 0($2)
-# was:	lw	_size_reg_4_, 0(_arr_reg_5_)
-	ori	$6, $28, 0
-# was:	ori	_letBind_3_, $28, 0
-	sll	$3, $5, 2
-# was:	sll	_tmp_32_, _size_reg_4_, 2
+_safe_lab_35_:
+	ori	$7, $28, 0
+# was:	ori	_arr_reg_30_, $28, 0
+	sll	$3, $2, 2
+# was:	sll	_tmp_41_, _size_reg_34_, 2
 	addi	$3, $3, 4
-# was:	addi	_tmp_32_, _tmp_32_, 4
+# was:	addi	_tmp_41_, _tmp_41_, 4
 	add	$28, $28, $3
-# was:	add	$28, $28, _tmp_32_
-	sw	$5, 0($6)
-# was:	sw	_size_reg_4_, 0(_letBind_3_)
-	addi	$3, $6, 4
-# was:	addi	_addr_reg_17_, _letBind_3_, 4
-	addi	$2, $2, 4
-# was:	addi	_arr_reg_5_, _arr_reg_5_, 4
-	ori	$4, $0, 0
-# was:	ori	_i_reg_18_, $0, 0
-	ori	$7, $0, 0
-# was:	ori	_count_reg_8_, $0, 0
-_loop_beg_19_:
-	sub	$8, $4, $5
-# was:	sub	_tmp_reg_22_, _i_reg_18_, _size_reg_4_
-	bgez	$8, _loop_end_20_
-# was:	bgez	_tmp_reg_22_, _loop_end_20_
-	lw	$10, 0($2)
-# was:	lw	_elem_reg_6_, 0(_arr_reg_5_)
-	addi	$2, $2, 4
-# was:	addi	_arr_reg_5_, _arr_reg_5_, 4
-# 	ori	_eq_L_24_,_elem_reg_6_,0
-	ori	$9, $10, 0
-# was:	ori	_div1_L_28_, _elem_reg_6_, 0
-	ori	$8, $0, 2
-# was:	ori	_div2_R_29_, $0, 2
-	bne	$8, $0, _safe_div_30_
-# was:	bne	_div2_R_29_, $0, _safe_div_30_
-	ori	$5, $0, 10
-# was:	ori	$5, $0, 10
-	la	$6, _Msg_DivZero_
-# was:	la	$6, _Msg_DivZero_
-	j	_RuntimeError_
-_safe_div_30_:
-	div	$8, $9, $8
-# was:	div	_mult1_L_26_, _div1_L_28_, _div2_R_29_
-	ori	$9, $0, 2
-# was:	ori	_mult2_R_27_, $0, 2
-	mul	$8, $8, $9
-# was:	mul	_eq_R_25_, _mult1_L_26_, _mult2_R_27_
-	ori	$9, $0, 0
-# was:	ori	_fun_arg_res_23_, $0, 0
-	bne	$10, $8, _false_31_
-# was:	bne	_eq_L_24_, _eq_R_25_, _false_31_
-	ori	$9, $0, 1
-# was:	ori	_fun_arg_res_23_, $0, 1
-_false_31_:
-# 	ori	_bool_reg_7_,_fun_arg_res_23_,0
-	beq	$9, $0, _if_end_21_
-# was:	beq	_bool_reg_7_, $0, _if_end_21_
-	sw	$10, 0($3)
-# was:	sw	_elem_reg_6_, 0(_addr_reg_17_)
-	addi	$3, $3, 4
-# was:	addi	_addr_reg_17_, _addr_reg_17_, 4
-	addi	$7, $7, 1
-# was:	addi	_count_reg_8_, _count_reg_8_, 1
-_if_end_21_:
-	addi	$4, $4, 1
-# was:	addi	_i_reg_18_, _i_reg_18_, 1
-	j	_loop_beg_19_
-_loop_end_20_:
-	sw	$7, 0($6)
-# was:	sw	_count_reg_8_, 0(_letBind_3_)
-	ori	$2, $6, 0
-# was:	ori	_arr_reg_35_, _letBind_3_, 0
-	lw	$3, 0($2)
-# was:	lw	_size_reg_34_, 0(_arr_reg_35_)
-	ori	$4, $28, 0
-# was:	ori	_letBind_33_, $28, 0
-	sll	$5, $3, 2
-# was:	sll	_tmp_46_, _size_reg_34_, 2
-	addi	$5, $5, 4
-# was:	addi	_tmp_46_, _tmp_46_, 4
-	add	$28, $28, $5
-# was:	add	$28, $28, _tmp_46_
-	sw	$3, 0($4)
-# was:	sw	_size_reg_34_, 0(_letBind_33_)
-	addi	$6, $4, 4
-# was:	addi	_addr_reg_38_, _letBind_33_, 4
+# was:	add	$28, $28, _tmp_41_
+	sw	$2, 0($7)
+# was:	sw	_size_reg_34_, 0(_arr_reg_30_)
+	addi	$3, $7, 4
+# was:	addi	_addr_reg_36_, _arr_reg_30_, 4
 	ori	$5, $0, 0
-# was:	ori	_i_reg_39_, $0, 0
-	addi	$2, $2, 4
-# was:	addi	_elem_reg_36_, _arr_reg_35_, 4
-_loop_beg_40_:
-	sub	$7, $5, $3
-# was:	sub	_tmp_reg_42_, _i_reg_39_, _size_reg_34_
-	bgez	$7, _loop_end_41_
-# was:	bgez	_tmp_reg_42_, _loop_end_41_
-	lw	$7, 0($2)
-# was:	lw	_res_reg_37_, 0(_elem_reg_36_)
-	addi	$2, $2, 4
-# was:	addi	_elem_reg_36_, _elem_reg_36_, 4
-	ori	$8, $7, 0
-# was:	ori	_mult1_L_44_, _res_reg_37_, 0
-# 	ori	_mult2_R_45_,_res_reg_37_,0
-	mul	$7, $8, $7
-# was:	mul	_fun_arg_res_43_, _mult1_L_44_, _mult2_R_45_
-# 	ori	_res_reg_37_,_fun_arg_res_43_,0
-	sw	$7, 0($6)
-# was:	sw	_res_reg_37_, 0(_addr_reg_38_)
-	addi	$6, $6, 4
-# was:	addi	_addr_reg_38_, _addr_reg_38_, 4
+# was:	ori	_i_reg_37_, $0, 0
+_loop_beg_38_:
+	sub	$4, $5, $2
+# was:	sub	_tmp_reg_40_, _i_reg_37_, _size_reg_34_
+	bgez	$4, _loop_end_39_
+# was:	bgez	_tmp_reg_40_, _loop_end_39_
+	sw	$5, 0($3)
+# was:	sw	_i_reg_37_, 0(_addr_reg_36_)
+	addi	$3, $3, 4
+# was:	addi	_addr_reg_36_, _addr_reg_36_, 4
 	addi	$5, $5, 1
-# was:	addi	_i_reg_39_, _i_reg_39_, 1
-	j	_loop_beg_40_
-_loop_end_41_:
-	ori	$2, $4, 0
-# was:	ori	_arr_reg_49_, _letBind_33_, 0
-	lw	$3, 0($2)
-# was:	lw	_size_reg_48_, 0(_arr_reg_49_)
-	ori	$4, $28, 0
-# was:	ori	_letBind_47_, $28, 0
-	sll	$5, $3, 2
-# was:	sll	_tmp_68_, _size_reg_48_, 2
-	addi	$5, $5, 4
-# was:	addi	_tmp_68_, _tmp_68_, 4
-	add	$28, $28, $5
-# was:	add	$28, $28, _tmp_68_
-	sw	$3, 0($4)
-# was:	sw	_size_reg_48_, 0(_letBind_47_)
-	addi	$5, $4, 4
-# was:	addi	_addr_reg_53_, _letBind_47_, 4
-	addi	$2, $2, 4
-# was:	addi	_arr_reg_49_, _arr_reg_49_, 4
+# was:	addi	_i_reg_37_, _i_reg_37_, 1
+	j	_loop_beg_38_
+_loop_end_39_:
+	lw	$3, 0($7)
+# was:	lw	_size_reg_29_, 0(_arr_reg_30_)
+	ori	$2, $28, 0
+# was:	ori	_letBind_28_, $28, 0
+	sll	$4, $3, 2
+# was:	sll	_tmp_57_, _size_reg_29_, 2
+	addi	$4, $4, 4
+# was:	addi	_tmp_57_, _tmp_57_, 4
+	add	$28, $28, $4
+# was:	add	$28, $28, _tmp_57_
+	sw	$3, 0($2)
+# was:	sw	_size_reg_29_, 0(_letBind_28_)
+	addi	$4, $2, 4
+# was:	addi	_addr_reg_42_, _letBind_28_, 4
 	ori	$6, $0, 0
-# was:	ori	_i_reg_54_, $0, 0
-	ori	$7, $0, 0
-# was:	ori	_count_reg_52_, $0, 0
-_loop_beg_55_:
+# was:	ori	_i_reg_43_, $0, 0
+	ori	$5, $0, 0
+# was:	ori	_j_reg_44_, $0, 0
+	addi	$7, $7, 4
+# was:	addi	_elem_reg_31_, _arr_reg_30_, 4
+_loop_beg_45_:
 	sub	$8, $6, $3
-# was:	sub	_tmp_reg_58_, _i_reg_54_, _size_reg_48_
-	bgez	$8, _loop_end_56_
-# was:	bgez	_tmp_reg_58_, _loop_end_56_
-	lw	$8, 0($2)
-# was:	lw	_elem_reg_50_, 0(_arr_reg_49_)
-	addi	$2, $2, 4
-# was:	addi	_arr_reg_49_, _arr_reg_49_, 4
-# 	ori	_div1_L_64_,_elem_reg_50_,0
-	ori	$9, $0, 16
-# was:	ori	_div2_R_65_, $0, 16
-	bne	$9, $0, _safe_div_66_
-# was:	bne	_div2_R_65_, $0, _safe_div_66_
-	ori	$5, $0, 6
-# was:	ori	$5, $0, 6
-	la	$6, _Msg_DivZero_
-# was:	la	$6, _Msg_DivZero_
-	j	_RuntimeError_
-_safe_div_66_:
-	div	$10, $8, $9
-# was:	div	_mult1_L_62_, _div1_L_64_, _div2_R_65_
-	ori	$9, $0, 16
-# was:	ori	_mult2_R_63_, $0, 16
-	mul	$10, $10, $9
-# was:	mul	_eq_L_60_, _mult1_L_62_, _mult2_R_63_
-# 	ori	_eq_R_61_,_elem_reg_50_,0
-	ori	$9, $0, 0
-# was:	ori	_fun_arg_res_59_, $0, 0
-	bne	$10, $8, _false_67_
-# was:	bne	_eq_L_60_, _eq_R_61_, _false_67_
-	ori	$9, $0, 1
-# was:	ori	_fun_arg_res_59_, $0, 1
-_false_67_:
-# 	ori	_bool_reg_51_,_fun_arg_res_59_,0
-	beq	$9, $0, _if_end_57_
-# was:	beq	_bool_reg_51_, $0, _if_end_57_
-	sw	$8, 0($5)
-# was:	sw	_elem_reg_50_, 0(_addr_reg_53_)
-	addi	$5, $5, 4
-# was:	addi	_addr_reg_53_, _addr_reg_53_, 4
-	addi	$7, $7, 1
-# was:	addi	_count_reg_52_, _count_reg_52_, 1
-_if_end_57_:
+# was:	sub	_tmp_reg_48_, _i_reg_43_, _size_reg_29_
+	bgez	$8, _loop_end_46_
+# was:	bgez	_tmp_reg_48_, _loop_end_46_
+	lw	$10, 0($7)
+# was:	lw	_res_reg_32_, 0(_elem_reg_31_)
+	addi	$7, $7, 4
+# was:	addi	_elem_reg_31_, _elem_reg_31_, 4
+# 	ori	_eq_L_50_,_res_reg_32_,0
+	ori	$9, $10, 0
+# was:	ori	_divide_L_54_, _res_reg_32_, 0
+	ori	$8, $0, 2
+# was:	ori	_divide_R_55_, $0, 2
+	div	$8, $9, $8
+# was:	div	_times_L_52_, _divide_L_54_, _divide_R_55_
+	ori	$9, $0, 2
+# was:	ori	_times_R_53_, $0, 2
+	mul	$9, $8, $9
+# was:	mul	_eq_R_51_, _times_L_52_, _times_R_53_
+	ori	$8, $0, 0
+# was:	ori	_fun_arg_res_49_, $0, 0
+	bne	$10, $9, _false_56_
+# was:	bne	_eq_L_50_, _eq_R_51_, _false_56_
+	ori	$8, $0, 1
+# was:	ori	_fun_arg_res_49_, $0, 1
+_false_56_:
+# 	ori	_bool_reg_33_,_fun_arg_res_49_,0
+	beq	$8, $0, _not_true_47_
+# was:	beq	_bool_reg_33_, $0, _not_true_47_
+	sw	$10, 0($4)
+# was:	sw	_res_reg_32_, 0(_addr_reg_42_)
+	addi	$5, $5, 1
+# was:	addi	_j_reg_44_, _j_reg_44_, 1
+	addi	$4, $4, 4
+# was:	addi	_addr_reg_42_, _addr_reg_42_, 4
+_not_true_47_:
 	addi	$6, $6, 1
-# was:	addi	_i_reg_54_, _i_reg_54_, 1
-	j	_loop_beg_55_
-_loop_end_56_:
-	sw	$7, 0($4)
-# was:	sw	_count_reg_52_, 0(_letBind_47_)
-# 	ori	_arr_reg_70_,_letBind_47_,0
-	lw	$16, 0($4)
-# was:	lw	_size_reg_69_, 0(_arr_reg_70_)
-	ori	$17, $28, 0
-# was:	ori	_mainres_1_, $28, 0
-	sll	$2, $16, 2
-# was:	sll	_tmp_80_, _size_reg_69_, 2
+# was:	addi	_i_reg_43_, _i_reg_43_, 1
+	j	_loop_beg_45_
+_loop_end_46_:
+	sw	$5, 0($2)
+# was:	sw	_j_reg_44_, 0(_letBind_28_)
+# 	ori	_arr_reg_60_,_letBind_28_,0
+	lw	$5, 0($2)
+# was:	lw	_size_reg_59_, 0(_arr_reg_60_)
+	ori	$4, $28, 0
+# was:	ori	_letBind_58_, $28, 0
+	sll	$3, $5, 2
+# was:	sll	_tmp_71_, _size_reg_59_, 2
+	addi	$3, $3, 4
+# was:	addi	_tmp_71_, _tmp_71_, 4
+	add	$28, $28, $3
+# was:	add	$28, $28, _tmp_71_
+	sw	$5, 0($4)
+# was:	sw	_size_reg_59_, 0(_letBind_58_)
+	addi	$7, $4, 4
+# was:	addi	_addr_reg_63_, _letBind_58_, 4
+	ori	$6, $0, 0
+# was:	ori	_i_reg_64_, $0, 0
+	addi	$3, $2, 4
+# was:	addi	_elem_reg_61_, _arr_reg_60_, 4
+_loop_beg_65_:
+	sub	$2, $6, $5
+# was:	sub	_tmp_reg_67_, _i_reg_64_, _size_reg_59_
+	bgez	$2, _loop_end_66_
+# was:	bgez	_tmp_reg_67_, _loop_end_66_
+	lw	$2, 0($3)
+# was:	lw	_res_reg_62_, 0(_elem_reg_61_)
+	addi	$3, $3, 4
+# was:	addi	_elem_reg_61_, _elem_reg_61_, 4
+	ori	$8, $2, 0
+# was:	ori	_times_L_69_, _res_reg_62_, 0
+# 	ori	_times_R_70_,_res_reg_62_,0
+	mul	$2, $8, $2
+# was:	mul	_fun_arg_res_68_, _times_L_69_, _times_R_70_
+# 	ori	_res_reg_62_,_fun_arg_res_68_,0
+	sw	$2, 0($7)
+# was:	sw	_res_reg_62_, 0(_addr_reg_63_)
+	addi	$7, $7, 4
+# was:	addi	_addr_reg_63_, _addr_reg_63_, 4
+	addi	$6, $6, 1
+# was:	addi	_i_reg_64_, _i_reg_64_, 1
+	j	_loop_beg_65_
+_loop_end_66_:
+# 	ori	_arr_reg_74_,_letBind_58_,0
+	lw	$17, 0($4)
+# was:	lw	_size_reg_73_, 0(_arr_reg_74_)
+	ori	$16, $28, 0
+# was:	ori	_letBind_72_, $28, 0
+	sll	$2, $17, 2
+# was:	sll	_tmp_86_, _size_reg_73_, 2
 	addi	$2, $2, 4
-# was:	addi	_tmp_80_, _tmp_80_, 4
+# was:	addi	_tmp_86_, _tmp_86_, 4
 	add	$28, $28, $2
-# was:	add	$28, $28, _tmp_80_
-	sw	$16, 0($17)
-# was:	sw	_size_reg_69_, 0(_mainres_1_)
-	addi	$18, $17, 4
-# was:	addi	_addr_reg_73_, _mainres_1_, 4
-	ori	$19, $0, 0
-# was:	ori	_i_reg_74_, $0, 0
-	addi	$20, $4, 4
-# was:	addi	_elem_reg_71_, _arr_reg_70_, 4
-_loop_beg_75_:
-	sub	$2, $19, $16
-# was:	sub	_tmp_reg_77_, _i_reg_74_, _size_reg_69_
-	bgez	$2, _loop_end_76_
-# was:	bgez	_tmp_reg_77_, _loop_end_76_
-	lw	$21, 0($20)
-# was:	lw	_res_reg_72_, 0(_elem_reg_71_)
-	addi	$20, $20, 4
-# was:	addi	_elem_reg_71_, _elem_reg_71_, 4
-# 	ori	_tmp_79_,_res_reg_72_,0
-# 	ori	_fun_arg_res_78_,_tmp_79_,0
-	ori	$2, $21, 0
-# was:	ori	$2, _fun_arg_res_78_, 0
-	jal	putint
-# was:	jal	putint, $2
-# 	ori	_res_reg_72_,_fun_arg_res_78_,0
-	sw	$21, 0($18)
-# was:	sw	_res_reg_72_, 0(_addr_reg_73_)
-	addi	$18, $18, 4
-# was:	addi	_addr_reg_73_, _addr_reg_73_, 4
-	addi	$19, $19, 1
-# was:	addi	_i_reg_74_, _i_reg_74_, 1
-	j	_loop_beg_75_
-_loop_end_76_:
-	ori	$2, $17, 0
-# was:	ori	$2, _mainres_1_, 0
-	addi	$29, $29, 32
+# was:	add	$28, $28, _tmp_86_
+	sw	$17, 0($16)
+# was:	sw	_size_reg_73_, 0(_letBind_72_)
+	addi	$19, $16, 4
+# was:	addi	_addr_reg_78_, _letBind_72_, 4
+	ori	$18, $0, 0
+# was:	ori	_i_reg_79_, $0, 0
+	ori	$20, $0, 0
+# was:	ori	_j_reg_80_, $0, 0
+	addi	$21, $4, 4
+# was:	addi	_elem_reg_75_, _arr_reg_74_, 4
+_loop_beg_81_:
+	sub	$2, $18, $17
+# was:	sub	_tmp_reg_84_, _i_reg_79_, _size_reg_73_
+	bgez	$2, _loop_end_82_
+# was:	bgez	_tmp_reg_84_, _loop_end_82_
+	lw	$22, 0($21)
+# was:	lw	_res_reg_76_, 0(_elem_reg_75_)
+	addi	$21, $21, 4
+# was:	addi	_elem_reg_75_, _elem_reg_75_, 4
+	ori	$2, $22, 0
+# was:	ori	$2, _res_reg_76_, 0
+	jal	isMul16
+# was:	jal	isMul16, $2
+# 	ori	_tmp_reg_85_,$2,0
+# 	ori	_bool_reg_77_,_tmp_reg_85_,0
+	beq	$2, $0, _not_true_83_
+# was:	beq	_bool_reg_77_, $0, _not_true_83_
+	sw	$22, 0($19)
+# was:	sw	_res_reg_76_, 0(_addr_reg_78_)
+	addi	$20, $20, 1
+# was:	addi	_j_reg_80_, _j_reg_80_, 1
+	addi	$19, $19, 4
+# was:	addi	_addr_reg_78_, _addr_reg_78_, 4
+_not_true_83_:
+	addi	$18, $18, 1
+# was:	addi	_i_reg_79_, _i_reg_79_, 1
+	j	_loop_beg_81_
+_loop_end_82_:
+	sw	$20, 0($16)
+# was:	sw	_j_reg_80_, 0(_letBind_72_)
+	ori	$2, $16, 0
+# was:	ori	_arg_87_, _letBind_72_, 0
+# 	ori	$2,_arg_87_,0
+	jal	write_int_arr
+# was:	jal	write_int_arr, $2
+# 	ori	_mainres_26_,$2,0
+# 	ori	$2,_mainres_26_,0
+	addi	$29, $29, 36
+	lw	$22, -32($29)
 	lw	$21, -28($29)
 	lw	$20, -24($29)
 	lw	$19, -20($29)
diff --git a/tests/replicate.asm b/tests/replicate.asm
index a6af3d4..5291a7a 100644
--- a/tests/replicate.asm
+++ b/tests/replicate.asm
@@ -17,115 +17,126 @@
 _stop_:
 	ori	$2, $0, 10
 	syscall
+# Function writeBool
+writeBool:
+	sw	$31, -4($29)
+	sw	$16, -8($29)
+	addi	$29, $29, -12
+# 	ori	_param_b_1_,$2,0
+	ori	$16, $2, 0
+# was:	ori	_tmp_3_, _param_b_1_, 0
+# 	ori	_writeBoolres_2_,_tmp_3_,0
+	la	$2, _true
+# was:	la	$2, _true
+	bne	$16, $0, _wBoolF_4_
+# was:	bne	_writeBoolres_2_, $0, _wBoolF_4_
+	la	$2, _false
+# was:	la	$2, _false
+_wBoolF_4_:
+	jal	putstring
+# was:	jal	putstring, $2
+	ori	$2, $16, 0
+# was:	ori	$2, _writeBoolres_2_, 0
+	addi	$29, $29, 12
+	lw	$16, -8($29)
+	lw	$31, -4($29)
+	jr	$31
 # Function main
 main:
 	sw	$31, -4($29)
-	sw	$21, -28($29)
 	sw	$20, -24($29)
 	sw	$19, -20($29)
 	sw	$18, -16($29)
 	sw	$17, -12($29)
 	sw	$16, -8($29)
-	addi	$29, $29, -32
+	addi	$29, $29, -28
 	ori	$2, $0, 7
-# was:	ori	_size_reg_3_, $0, 7
-	bgez	$2, _safe_lab_4_
-# was:	bgez	_size_reg_3_, _safe_lab_4_
+# was:	ori	_size_reg_7_, $0, 7
+	ori	$7, $0, 0
+# was:	ori	_a_reg_8_, $0, 0
+	bgez	$2, _safe_lab_9_
+# was:	bgez	_size_reg_7_, _safe_lab_9_
 	ori	$5, $0, 4
 # was:	ori	$5, $0, 4
 	la	$6, _Msg_IllegalArraySize_
 # was:	la	$6, _Msg_IllegalArraySize_
 	j	_RuntimeError_
-_safe_lab_4_:
-	ori	$7, $0, 0
-# was:	ori	_elem_reg_5_, $0, 0
+_safe_lab_9_:
 	ori	$3, $28, 0
-# was:	ori	_letBind_2_, $28, 0
-	addi	$4, $2, 3
-# was:	addi	_tmp_11_, _size_reg_3_, 3
-	sra	$4, $4, 2
-# was:	sra	_tmp_11_, _tmp_11_, 2
-	sll	$4, $4, 2
-# was:	sll	_tmp_11_, _tmp_11_, 2
+# was:	ori	_letBind_6_, $28, 0
+	sll	$4, $2, 2
+# was:	sll	_tmp_15_, _size_reg_7_, 2
 	addi	$4, $4, 4
-# was:	addi	_tmp_11_, _tmp_11_, 4
+# was:	addi	_tmp_15_, _tmp_15_, 4
 	add	$28, $28, $4
-# was:	add	$28, $28, _tmp_11_
+# was:	add	$28, $28, _tmp_15_
 	sw	$2, 0($3)
-# was:	sw	_size_reg_3_, 0(_letBind_2_)
-	addi	$4, $3, 4
-# was:	addi	_addr_reg_6_, _letBind_2_, 4
+# was:	sw	_size_reg_7_, 0(_letBind_6_)
+	addi	$6, $3, 4
+# was:	addi	_addr_reg_10_, _letBind_6_, 4
 	ori	$5, $0, 0
-# was:	ori	_i_reg_7_, $0, 0
-_loop_beg_8_:
-	sub	$6, $5, $2
-# was:	sub	_tmp_reg_10_, _i_reg_7_, _size_reg_3_
-	bgez	$6, _loop_end_9_
-# was:	bgez	_tmp_reg_10_, _loop_end_9_
-	sb	$7, 0($4)
-# was:	sb	_elem_reg_5_, 0(_addr_reg_6_)
-	addi	$4, $4, 1
-# was:	addi	_addr_reg_6_, _addr_reg_6_, 1
+# was:	ori	_i_reg_11_, $0, 0
+_loop_beg_12_:
+	sub	$4, $5, $2
+# was:	sub	_tmp_reg_14_, _i_reg_11_, _size_reg_7_
+	bgez	$4, _loop_end_13_
+# was:	bgez	_tmp_reg_14_, _loop_end_13_
+	sb	$7, 0($6)
+# was:	sb	_a_reg_8_, 0(_addr_reg_10_)
+	addi	$6, $6, 4
+# was:	addi	_addr_reg_10_, _addr_reg_10_, 4
 	addi	$5, $5, 1
-# was:	addi	_i_reg_7_, _i_reg_7_, 1
-	j	_loop_beg_8_
-_loop_end_9_:
-# 	ori	_arr_reg_13_,_letBind_2_,0
+# was:	addi	_i_reg_11_, _i_reg_11_, 1
+	j	_loop_beg_12_
+_loop_end_13_:
+# 	ori	_arr_reg_17_,_letBind_6_,0
 	lw	$16, 0($3)
-# was:	lw	_size_reg_12_, 0(_arr_reg_13_)
+# was:	lw	_size_reg_16_, 0(_arr_reg_17_)
 	ori	$17, $28, 0
-# was:	ori	_mainres_1_, $28, 0
+# was:	ori	_mainres_5_, $28, 0
 	addi	$2, $16, 3
-# was:	addi	_tmp_24_, _size_reg_12_, 3
+# was:	addi	_tmp_26_, _size_reg_16_, 3
 	sra	$2, $2, 2
-# was:	sra	_tmp_24_, _tmp_24_, 2
+# was:	sra	_tmp_26_, _tmp_26_, 2
 	sll	$2, $2, 2
-# was:	sll	_tmp_24_, _tmp_24_, 2
+# was:	sll	_tmp_26_, _tmp_26_, 2
 	addi	$2, $2, 4
-# was:	addi	_tmp_24_, _tmp_24_, 4
+# was:	addi	_tmp_26_, _tmp_26_, 4
 	add	$28, $28, $2
-# was:	add	$28, $28, _tmp_24_
+# was:	add	$28, $28, _tmp_26_
 	sw	$16, 0($17)
-# was:	sw	_size_reg_12_, 0(_mainres_1_)
-	addi	$19, $17, 4
-# was:	addi	_addr_reg_16_, _mainres_1_, 4
-	ori	$18, $0, 0
-# was:	ori	_i_reg_17_, $0, 0
+# was:	sw	_size_reg_16_, 0(_mainres_5_)
+	addi	$18, $17, 4
+# was:	addi	_addr_reg_20_, _mainres_5_, 4
+	ori	$19, $0, 0
+# was:	ori	_i_reg_21_, $0, 0
 	addi	$20, $3, 4
-# was:	addi	_elem_reg_14_, _arr_reg_13_, 4
-_loop_beg_18_:
-	sub	$2, $18, $16
-# was:	sub	_tmp_reg_20_, _i_reg_17_, _size_reg_12_
-	bgez	$2, _loop_end_19_
-# was:	bgez	_tmp_reg_20_, _loop_end_19_
-	lb	$21, 0($20)
-# was:	lb	_res_reg_15_, 0(_elem_reg_14_)
+# was:	addi	_elem_reg_18_, _arr_reg_17_, 4
+_loop_beg_22_:
+	sub	$2, $19, $16
+# was:	sub	_tmp_reg_24_, _i_reg_21_, _size_reg_16_
+	bgez	$2, _loop_end_23_
+# was:	bgez	_tmp_reg_24_, _loop_end_23_
+	lb	$2, 0($20)
+# was:	lb	_res_reg_19_, 0(_elem_reg_18_)
 	addi	$20, $20, 1
-# was:	addi	_elem_reg_14_, _elem_reg_14_, 1
-# 	ori	_tmp_22_,_res_reg_15_,0
-# 	ori	_fun_arg_res_21_,_tmp_22_,0
-	la	$2, _true
-# was:	la	$2, _true
-	bne	$21, $0, _wBoolF_23_
-# was:	bne	_fun_arg_res_21_, $0, _wBoolF_23_
-	la	$2, _false
-# was:	la	$2, _false
-_wBoolF_23_:
-	jal	putstring
-# was:	jal	putstring, $2
-# 	ori	_res_reg_15_,_fun_arg_res_21_,0
-	sb	$21, 0($19)
-# was:	sb	_res_reg_15_, 0(_addr_reg_16_)
-	addi	$19, $19, 1
-# was:	addi	_addr_reg_16_, _addr_reg_16_, 1
+# was:	addi	_elem_reg_18_, _elem_reg_18_, 1
+# 	ori	$2,_res_reg_19_,0
+	jal	writeBool
+# was:	jal	writeBool, $2
+# 	ori	_tmp_reg_25_,$2,0
+# 	ori	_res_reg_19_,_tmp_reg_25_,0
+	sb	$2, 0($18)
+# was:	sb	_res_reg_19_, 0(_addr_reg_20_)
 	addi	$18, $18, 1
-# was:	addi	_i_reg_17_, _i_reg_17_, 1
-	j	_loop_beg_18_
-_loop_end_19_:
+# was:	addi	_addr_reg_20_, _addr_reg_20_, 1
+	addi	$19, $19, 1
+# was:	addi	_i_reg_21_, _i_reg_21_, 1
+	j	_loop_beg_22_
+_loop_end_23_:
 	ori	$2, $17, 0
-# was:	ori	$2, _mainres_1_, 0
-	addi	$29, $29, 32
-	lw	$21, -28($29)
+# was:	ori	$2, _mainres_5_, 0
+	addi	$29, $29, 28
 	lw	$20, -24($29)
 	lw	$19, -20($29)
 	lw	$18, -16($29)
diff --git a/tests/scan.asm b/tests/scan.asm
index 665ad98..99def1b 100644
--- a/tests/scan.asm
+++ b/tests/scan.asm
@@ -17,138 +17,169 @@
 _stop_:
 	ori	$2, $0, 10
 	syscall
+# Function incr
+incr:
+	sw	$31, -4($29)
+	addi	$29, $29, -8
+# 	ori	_param_a_1_,$2,0
+# 	ori	_param_b_2_,$3,0
+# 	ori	_plus_L_4_,_param_a_1_,0
+# 	ori	_plus_R_5_,_param_b_2_,0
+	add	$2, $2, $3
+# was:	add	_incrres_3_, _plus_L_4_, _plus_R_5_
+# 	ori	$2,_incrres_3_,0
+	addi	$29, $29, 8
+	lw	$31, -4($29)
+	jr	$31
+# Function writeInt
+writeInt:
+	sw	$31, -4($29)
+	sw	$16, -8($29)
+	addi	$29, $29, -12
+# 	ori	_param_n_6_,$2,0
+	ori	$16, $2, 0
+# was:	ori	_tmp_8_, _param_n_6_, 0
+# 	ori	_writeIntres_7_,_tmp_8_,0
+	ori	$2, $16, 0
+# was:	ori	$2, _writeIntres_7_, 0
+	jal	putint
+# was:	jal	putint, $2
+	ori	$2, $16, 0
+# was:	ori	$2, _writeIntres_7_, 0
+	addi	$29, $29, 12
+	lw	$16, -8($29)
+	lw	$31, -4($29)
+	jr	$31
 # Function main
 main:
 	sw	$31, -4($29)
-	sw	$21, -28($29)
 	sw	$20, -24($29)
 	sw	$19, -20($29)
 	sw	$18, -16($29)
 	sw	$17, -12($29)
 	sw	$16, -8($29)
-	addi	$29, $29, -32
-	ori	$4, $0, 3
-# was:	ori	_size_reg_3_, $0, 3
-	ori	$3, $28, 0
-# was:	ori	_letBind_2_, $28, 0
-	sll	$2, $4, 2
-# was:	sll	_tmp_6_, _size_reg_3_, 2
-	addi	$2, $2, 4
-# was:	addi	_tmp_6_, _tmp_6_, 4
-	add	$28, $28, $2
-# was:	add	$28, $28, _tmp_6_
-	sw	$4, 0($3)
-# was:	sw	_size_reg_3_, 0(_letBind_2_)
-	addi	$4, $3, 4
-# was:	addi	_addr_reg_4_, _letBind_2_, 4
-	ori	$2, $0, 1
-# was:	ori	_tmp_reg_5_, $0, 1
-	sw	$2, 0($4)
-# was:	sw	_tmp_reg_5_, 0(_addr_reg_4_)
-	addi	$4, $4, 4
-# was:	addi	_addr_reg_4_, _addr_reg_4_, 4
-	ori	$2, $0, 2
-# was:	ori	_tmp_reg_5_, $0, 2
-	sw	$2, 0($4)
-# was:	sw	_tmp_reg_5_, 0(_addr_reg_4_)
-	addi	$4, $4, 4
-# was:	addi	_addr_reg_4_, _addr_reg_4_, 4
+	addi	$29, $29, -28
 	ori	$2, $0, 3
-# was:	ori	_tmp_reg_5_, $0, 3
-	sw	$2, 0($4)
-# was:	sw	_tmp_reg_5_, 0(_addr_reg_4_)
+# was:	ori	_size_reg_11_, $0, 3
+	ori	$3, $28, 0
+# was:	ori	_letBind_10_, $28, 0
+	sll	$4, $2, 2
+# was:	sll	_tmp_14_, _size_reg_11_, 2
 	addi	$4, $4, 4
-# was:	addi	_addr_reg_4_, _addr_reg_4_, 4
-# 	ori	_inp_reg_9_,_letBind_2_,0
-	ori	$8, $0, 0
-# was:	ori	_acc_reg_13_, $0, 0
-	lw	$4, 0($3)
-# was:	lw	_size_reg_10_, 0(_inp_reg_9_)
-	addi	$3, $3, 4
-# was:	addi	_inp_reg_9_, _inp_reg_9_, 4
-	ori	$2, $28, 0
-# was:	ori	_letBind_7_, $28, 0
-	sll	$5, $4, 2
-# was:	sll	_tmp_16_, _size_reg_10_, 2
-	addi	$5, $5, 4
-# was:	addi	_tmp_16_, _tmp_16_, 4
-	add	$28, $28, $5
-# was:	add	$28, $28, _tmp_16_
+# was:	addi	_tmp_14_, _tmp_14_, 4
+	add	$28, $28, $4
+# was:	add	$28, $28, _tmp_14_
+	sw	$2, 0($3)
+# was:	sw	_size_reg_11_, 0(_letBind_10_)
+	addi	$2, $3, 4
+# was:	addi	_addr_reg_12_, _letBind_10_, 4
+	ori	$4, $0, 1
+# was:	ori	_tmp_reg_13_, $0, 1
 	sw	$4, 0($2)
-# was:	sw	_size_reg_10_, 0(_letBind_7_)
-	addi	$6, $2, 4
-# was:	addi	_res_reg_8_, _letBind_7_, 4
-	ori	$5, $0, 0
-# was:	ori	_ind_var_11_, $0, 0
-_loop_beg_14_:
-	sub	$7, $5, $4
-# was:	sub	_tmp_reg_12_, _ind_var_11_, _size_reg_10_
-	bgez	$7, _loop_end_15_
-# was:	bgez	_tmp_reg_12_, _loop_end_15_
-	lw	$7, 0($3)
-# was:	lw	_tmp_reg_12_, 0(_inp_reg_9_)
-# 	ori	_plus_L_18_,_acc_reg_13_,0
-# 	ori	_plus_R_19_,_tmp_reg_12_,0
-	add	$8, $8, $7
-# was:	add	_fun_arg_res_17_, _plus_L_18_, _plus_R_19_
-# 	ori	_acc_reg_13_,_fun_arg_res_17_,0
-	sw	$8, 0($6)
-# was:	sw	_acc_reg_13_, 0(_res_reg_8_)
-	addi	$6, $6, 4
-# was:	addi	_res_reg_8_, _res_reg_8_, 4
-	addi	$3, $3, 4
-# was:	addi	_inp_reg_9_, _inp_reg_9_, 4
-	addi	$5, $5, 1
-# was:	addi	_ind_var_11_, _ind_var_11_, 1
-	j	_loop_beg_14_
-_loop_end_15_:
-# 	ori	_arr_reg_21_,_letBind_7_,0
-	lw	$17, 0($2)
-# was:	lw	_size_reg_20_, 0(_arr_reg_21_)
+# was:	sw	_tmp_reg_13_, 0(_addr_reg_12_)
+	addi	$2, $2, 4
+# was:	addi	_addr_reg_12_, _addr_reg_12_, 4
+	ori	$4, $0, 2
+# was:	ori	_tmp_reg_13_, $0, 2
+	sw	$4, 0($2)
+# was:	sw	_tmp_reg_13_, 0(_addr_reg_12_)
+	addi	$2, $2, 4
+# was:	addi	_addr_reg_12_, _addr_reg_12_, 4
+	ori	$4, $0, 3
+# was:	ori	_tmp_reg_13_, $0, 3
+	sw	$4, 0($2)
+# was:	sw	_tmp_reg_13_, 0(_addr_reg_12_)
+	addi	$2, $2, 4
+# was:	addi	_addr_reg_12_, _addr_reg_12_, 4
+# 	ori	_arr_reg_17_,_letBind_10_,0
+	ori	$2, $0, 0
+# was:	ori	_nelem_reg_20_, $0, 0
+	lw	$17, 0($3)
+# was:	lw	_size_reg_16_, 0(_arr_reg_17_)
 	ori	$16, $28, 0
-# was:	ori	_mainres_1_, $28, 0
-	sll	$3, $17, 2
-# was:	sll	_tmp_31_, _size_reg_20_, 2
-	addi	$3, $3, 4
-# was:	addi	_tmp_31_, _tmp_31_, 4
-	add	$28, $28, $3
-# was:	add	$28, $28, _tmp_31_
+# was:	ori	_letBind_15_, $28, 0
+	sll	$4, $17, 2
+# was:	sll	_tmp_27_, _size_reg_16_, 2
+	addi	$4, $4, 4
+# was:	addi	_tmp_27_, _tmp_27_, 4
+	add	$28, $28, $4
+# was:	add	$28, $28, _tmp_27_
 	sw	$17, 0($16)
-# was:	sw	_size_reg_20_, 0(_mainres_1_)
-	addi	$18, $16, 4
-# was:	addi	_addr_reg_24_, _mainres_1_, 4
-	ori	$19, $0, 0
-# was:	ori	_i_reg_25_, $0, 0
-	addi	$20, $2, 4
-# was:	addi	_elem_reg_22_, _arr_reg_21_, 4
-_loop_beg_26_:
-	sub	$2, $19, $17
-# was:	sub	_tmp_reg_28_, _i_reg_25_, _size_reg_20_
-	bgez	$2, _loop_end_27_
-# was:	bgez	_tmp_reg_28_, _loop_end_27_
-	lw	$21, 0($20)
-# was:	lw	_res_reg_23_, 0(_elem_reg_22_)
+# was:	sw	_size_reg_16_, 0(_letBind_15_)
+	addi	$19, $16, 4
+# was:	addi	_addr_reg_21_, _letBind_15_, 4
+	ori	$18, $0, 0
+# was:	ori	_i_reg_22_, $0, 0
+	addi	$20, $3, 4
+# was:	addi	_elem_reg_18_, _arr_reg_17_, 4
+_loop_beg_23_:
+	sub	$3, $18, $17
+# was:	sub	_tmp_reg_25_, _i_reg_22_, _size_reg_16_
+	bgez	$3, _loop_end_24_
+# was:	bgez	_tmp_reg_25_, _loop_end_24_
+	lw	$3, 0($20)
+# was:	lw	_res_reg_19_, 0(_elem_reg_18_)
 	addi	$20, $20, 4
-# was:	addi	_elem_reg_22_, _elem_reg_22_, 4
-# 	ori	_tmp_30_,_res_reg_23_,0
-# 	ori	_fun_arg_res_29_,_tmp_30_,0
-	ori	$2, $21, 0
-# was:	ori	$2, _fun_arg_res_29_, 0
-	jal	putint
-# was:	jal	putint, $2
-# 	ori	_res_reg_23_,_fun_arg_res_29_,0
-	sw	$21, 0($18)
-# was:	sw	_res_reg_23_, 0(_addr_reg_24_)
-	addi	$18, $18, 4
-# was:	addi	_addr_reg_24_, _addr_reg_24_, 4
-	addi	$19, $19, 1
-# was:	addi	_i_reg_25_, _i_reg_25_, 1
-	j	_loop_beg_26_
-_loop_end_27_:
+# was:	addi	_elem_reg_18_, _elem_reg_18_, 4
+# 	ori	$2,_nelem_reg_20_,0
+# 	ori	$3,_res_reg_19_,0
+	jal	incr
+# was:	jal	incr, $2 $3
+# 	ori	_tmp_reg_26_,$2,0
+# 	ori	_nelem_reg_20_,_tmp_reg_26_,0
+	sw	$2, 0($19)
+# was:	sw	_nelem_reg_20_, 0(_addr_reg_21_)
+	addi	$19, $19, 4
+# was:	addi	_addr_reg_21_, _addr_reg_21_, 4
+	addi	$18, $18, 1
+# was:	addi	_i_reg_22_, _i_reg_22_, 1
+	j	_loop_beg_23_
+_loop_end_24_:
 	ori	$2, $16, 0
-# was:	ori	$2, _mainres_1_, 0
-	addi	$29, $29, 32
-	lw	$21, -28($29)
+# was:	ori	_arr_reg_29_, _letBind_15_, 0
+	lw	$16, 0($2)
+# was:	lw	_size_reg_28_, 0(_arr_reg_29_)
+	ori	$17, $28, 0
+# was:	ori	_mainres_9_, $28, 0
+	sll	$3, $16, 2
+# was:	sll	_tmp_38_, _size_reg_28_, 2
+	addi	$3, $3, 4
+# was:	addi	_tmp_38_, _tmp_38_, 4
+	add	$28, $28, $3
+# was:	add	$28, $28, _tmp_38_
+	sw	$16, 0($17)
+# was:	sw	_size_reg_28_, 0(_mainres_9_)
+	addi	$18, $17, 4
+# was:	addi	_addr_reg_32_, _mainres_9_, 4
+	ori	$19, $0, 0
+# was:	ori	_i_reg_33_, $0, 0
+	addi	$20, $2, 4
+# was:	addi	_elem_reg_30_, _arr_reg_29_, 4
+_loop_beg_34_:
+	sub	$2, $19, $16
+# was:	sub	_tmp_reg_36_, _i_reg_33_, _size_reg_28_
+	bgez	$2, _loop_end_35_
+# was:	bgez	_tmp_reg_36_, _loop_end_35_
+	lw	$2, 0($20)
+# was:	lw	_res_reg_31_, 0(_elem_reg_30_)
+	addi	$20, $20, 4
+# was:	addi	_elem_reg_30_, _elem_reg_30_, 4
+# 	ori	$2,_res_reg_31_,0
+	jal	writeInt
+# was:	jal	writeInt, $2
+# 	ori	_tmp_reg_37_,$2,0
+# 	ori	_res_reg_31_,_tmp_reg_37_,0
+	sw	$2, 0($18)
+# was:	sw	_res_reg_31_, 0(_addr_reg_32_)
+	addi	$18, $18, 4
+# was:	addi	_addr_reg_32_, _addr_reg_32_, 4
+	addi	$19, $19, 1
+# was:	addi	_i_reg_33_, _i_reg_33_, 1
+	j	_loop_beg_34_
+_loop_end_35_:
+	ori	$2, $17, 0
+# was:	ori	$2, _mainres_9_, 0
+	addi	$29, $29, 28
 	lw	$20, -24($29)
 	lw	$19, -20($29)
 	lw	$18, -16($29)