264 lines
11 KiB
C
264 lines
11 KiB
C
#include <stddef.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include "support.h"
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#include "wires.h"
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#include "arithmetic.h"
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#include "memory.h"
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#include "registers.h"
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#include "ip_reg.h"
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#include "compute.h"
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// major opcodes
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#define RETURN_STOP 0x0
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#define REG_ARITHMETIC 0x1
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#define REG_MOVQ 0x2
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#define REG_MOVQ_MEM 0x3
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#define CFLOW 0x4
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#define IMM_ARITHMETIC 0x5
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#define IMM_MOVQ 0x6
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#define IMM_MOVQ_MEM 0x7
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#define LEAQ2 0x8
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#define LEAQ3 0x9
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#define LEAQ6 0xA
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#define LEAQ7 0xB
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#define IMM_CBRANCH 0xF
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// minor opcodes
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#define STOP 0x0
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#define RETURN 0x1
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#define JMP 0xF
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#define CALL 0xE
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int main(int argc, char* argv[]) {
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// Check command line parameters.
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if (argc < 2)
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error("missing name of programfile to simulate");
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if (argc < 3)
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error("Missing starting address (in hex notation)");
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/*** SETUP ***/
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// We set up global state through variables that are preserved between cycles.
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// Program counter / Instruction Pointer
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ip_reg_p ip = ip_reg_create();
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// Register file:
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reg_p regs = regs_create();
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// Memory:
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// Shared memory for both instructions and data.
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mem_p mem = memory_create();
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memory_read_from_file(mem, argv[1]);
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int start;
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int scan_res = sscanf(argv[2],"%x", &start);
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if (scan_res != 1)
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error("Unable to interpret starting address");
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// We must setup argv from commandline before enabling tracefile
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// validation.
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if (argc > 4) { // one or more additional arguments specified.
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if (strcmp(argv[3],"--") != 0)
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error("3rd arg must be '--' if additional args are provided");
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// arguments beyond '--' are loaded into argv area in memory
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memory_load_argv(mem, argc - 4, argv + 4);
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} else
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memory_load_argv(mem, 0, NULL);
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// memory is now set up correctly, and we can enable tracefile
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// validation if a tracefile has been specified.
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if (argc == 4) { // tracefile specified, hook memories to it
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memory_tracefile(mem, argv[3]);
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regs_tracefile(regs, argv[3]);
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ip_reg_tracefile(ip, argv[3]);
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}
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ip_write(ip, from_int(start), true);
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// a stop signal for stopping the simulation.
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bool stop = false;
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// We need the instruction number to show how far we get
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int instruction_number = 0;
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while (!stop) { // SIMULATION BEGINS - for each cycle:
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/*** FETCH ***/
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val pc = ip_read(ip);
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++instruction_number;
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printf("%d %lx\n", instruction_number, pc.val);
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// We're fetching 10 bytes in the form of 10 vals with one byte each
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// depending on the instruction we may not use all of them
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val inst_bytes[10];
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memory_read_into_buffer(mem, pc, inst_bytes, true);
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/*** DECODE ***/
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// read 4 bit segments of the instruction. The following 6 segments
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// are, if present, always located at the same position in the instruction
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val major_op = pick_bits(4, 4, inst_bytes[0]);
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val minor_op = pick_bits(0, 4, inst_bytes[0]);
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val reg_d = pick_bits(4, 4, inst_bytes[1]);
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val reg_s = pick_bits(0, 4, inst_bytes[1]);
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val reg_z = pick_bits(4, 4, inst_bytes[2]);
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val shamt = pick_bits(0, 4, inst_bytes[2]);
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val target = pick_bits(0, 8, inst_bytes[2]);
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// decode instruction type from major operation code
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bool is_return_or_stop = is(RETURN_STOP, major_op);
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bool is_reg_arithmetic = is(REG_ARITHMETIC, major_op);
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bool is_imm_arithmetic = is(IMM_ARITHMETIC, major_op);
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bool is_reg_movq = is(REG_MOVQ, major_op);
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bool is_imm_movq = is(IMM_MOVQ, major_op);
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bool is_reg_movq_mem = is(REG_MOVQ_MEM, major_op);
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bool is_imm_movq_mem = is(IMM_MOVQ_MEM, major_op);
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bool is_cflow = is(CFLOW, major_op); /* note that this signal does not include return - though logically it could */
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bool is_leaq2 = is(LEAQ2, major_op);
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bool is_leaq3 = is(LEAQ3, major_op);
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bool is_leaq6 = is(LEAQ6, major_op);
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bool is_leaq7 = is(LEAQ7, major_op);
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bool is_imm_cbranch = is(IMM_CBRANCH, major_op);
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// Right now, we can only execute instructions with a size of 2.
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// from info above determine the instruction size
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bool size_is_2 = (is_return_or_stop || is_reg_arithmetic || is_reg_movq || is_reg_movq_mem || is_leaq2);
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val size_2 = use_if(size_is_2, from_int(2));
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bool size_is_3 = (is_leaq3);
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val size_3 = use_if(size_is_3, from_int(3));
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bool size_is_6 = (is_cflow || is_imm_arithmetic || is_imm_movq || is_imm_movq_mem || is_leaq6);
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val size_6 = use_if(size_is_6, from_int(6));
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bool size_is_7 = (is_leaq7);
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val size_7 = use_if(size_is_7, from_int(7));
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bool size_is_10 = (is_imm_cbranch);
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val size_10 = use_if(size_is_10, from_int(10));
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val add_1 = add(size_2, size_3);
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val add_2 = add(add_1, size_6);
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val add_3 = add(add_2, size_7);
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val add_4 = add(add_3, size_10);
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val ins_size = add_4;
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// broad categorization of the instruction
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bool is_leaq = is_leaq2 || is_leaq3 || is_leaq6 || is_leaq7;
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bool is_move = is_reg_movq || is_reg_movq_mem || is_imm_movq || is_imm_movq_mem;
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bool is_mem_access = is_reg_movq_mem || is_imm_movq_mem;
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bool is_call = is_cflow && is(CALL, minor_op);
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bool is_return = is_return_or_stop & is(RETURN, minor_op);
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bool is_stop = is_return_or_stop & is(STOP, minor_op);
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// picking the proper immediate positions within the instruction:
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bool imm_i_pos3 = is_leaq7; /* all other at position 2 */
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bool imm_p_pos6 = is_imm_cbranch; /* all other at position 2 */
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// unimplemented control signals:
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bool is_load = (is_mem_access && !pick_one(3,minor_op));
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bool is_store = (is_mem_access && pick_one(3,minor_op));
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bool is_conditional = (is_cflow || is_imm_cbranch) && !(is(0xE, minor_op) || is(0xF, minor_op));
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// setting up operand fetch and register read and write for the datapath:
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bool use_imm = is_imm_movq | is_imm_arithmetic | is_imm_cbranch;
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val reg_read_dz = or(use_if(!is_leaq, reg_d), use_if(is_leaq, reg_z));
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// - other read port is always reg_s
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// - write is always to reg_d
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bool reg_wr_enable = is_reg_arithmetic || is_imm_arithmetic || is_leaq || is_load || is_reg_movq || is_imm_movq || is_call;
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// control signals for the compute section:
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// - pick result of compute section
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bool use_agen = is_leaq || is_move;
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bool is_arithmetic = is_imm_arithmetic | is_reg_arithmetic;
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bool use_multiplier = is_arithmetic && (is(MUL, minor_op) || is(IMUL, minor_op));
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bool use_shifter = is_arithmetic && (is(SAR, minor_op) || is(SAL, minor_op) || is(SHR, minor_op));
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bool use_direct = is_reg_movq || is_imm_movq;
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bool use_alu = (is_arithmetic || is_conditional) && !(use_shifter | use_multiplier);
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// - control for agen
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bool use_s = (is(1,pick_bits(0,1,minor_op)) && use_agen) || is_reg_arithmetic || is_cflow;
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bool use_z = is(1,pick_bits(1,1,minor_op)) && use_agen;
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bool use_d = (is(1,pick_bits(2,1,minor_op)) && use_agen) || is_imm_arithmetic || is_imm_cbranch;
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// - control for the ALU (too easy)
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val alu_ctrl = minor_op;
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// - control for the multiplier
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bool mul_is_signed = is(IMUL, minor_op);
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// - control for the shifter
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bool shft_is_signed = is(SAR, minor_op) | is(SAL, minor_op);
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bool shft_is_left = is(SAL, minor_op);
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/*** EXECUTE ***/
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// Datapath:
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//
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// read immediates based on instruction type from the instruction buffer
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val imm_offset_2 = or(or(put_bits(0, 8, inst_bytes[2]), put_bits(8,8, inst_bytes[3])),
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or(put_bits(16, 8, inst_bytes[4]), put_bits(24,8, inst_bytes[5])));
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val imm_offset_3 = or(or(put_bits(0, 8, inst_bytes[3]), put_bits(8,8, inst_bytes[4])),
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or(put_bits(16, 8, inst_bytes[5]), put_bits(24,8, inst_bytes[6])));
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val imm_offset_6 = or(or(put_bits(0, 8, inst_bytes[6]), put_bits(8,8, inst_bytes[7])),
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or(put_bits(16, 8, inst_bytes[8]), put_bits(24,8, inst_bytes[9])));
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val imm_i = or(use_if( !imm_i_pos3, imm_offset_2), use_if( imm_i_pos3, imm_offset_3));
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val imm_p = or(use_if( !imm_p_pos6, imm_offset_2), use_if( imm_p_pos6, imm_offset_6));
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val sext_imm_i = sign_extend(31, imm_i);
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val sext_imm_p = sign_extend(31, imm_p);
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// read registers
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val reg_out_a = reg_read(regs, reg_read_dz);
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val reg_out_b = reg_read(regs, reg_s);
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val op_b = or(use_if(use_imm, sext_imm_i), use_if(!use_imm, reg_out_b));
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// perform calculations
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val agen_result = address_generate(reg_out_a, reg_out_b, sext_imm_i,
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shamt, use_z, use_s, use_d);
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val alu_result = alu_execute(alu_ctrl, reg_out_a, op_b);
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val mul_result = multiplier(mul_is_signed, reg_out_a, op_b);
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val shifter_result = shifter(shft_is_left, shft_is_signed, reg_out_a, op_b);
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val compute_result = or(use_if(use_agen, agen_result),
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or(use_if(use_multiplier, mul_result),
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or(use_if(use_shifter, shifter_result),
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or(use_if(use_direct, op_b),
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use_if(use_alu, alu_result)))));
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// address of succeeding instruction in memory
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val pc_incremented = add(pc, ins_size);
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// determine the next position of the program counter
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bool is_jump = is_cflow && (is(0xF,minor_op) || (is_conditional && !reduce_or(compute_result)));
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val pc_next_if_not_control = use_if(!(is_jump || is_return), pc_incremented);
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val pc_next_if_jump = use_if(is_jump, target);
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val pc_next_if_return = use_if(is_return, reg_out_b);
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val pc_next = add(add(pc_next_if_not_control, pc_next_if_jump), pc_next_if_return);
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/*** MEMORY ***/
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// read from memory if needed
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val mem_out = memory_read(mem, agen_result, is_load);
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/*** WRITE ***/
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// choose result to write back to register
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bool use_compute_result = !is_load && (use_agen || use_multiplier || use_shifter || use_direct || use_alu);
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val datapath_result = or(use_if(use_compute_result, compute_result),
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use_if(is_load, mem_out));
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// write to register if needed
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reg_write(regs, reg_d, datapath_result, reg_wr_enable);
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// write to memory if needed
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memory_write(mem, agen_result, reg_out_a, is_store);
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// update program counter
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ip_write(ip, pc_next, true);
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// terminate when returning to zero
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if (is_stop || (pc_next.val == 0 && is_return)) stop = true;
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}
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memory_destroy(mem);
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regs_destroy(regs);
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printf("Done\n");
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}
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