diff --git a/A5/main.c b/A5/main.c index 95e60e6..295571f 100644 --- a/A5/main.c +++ b/A5/main.c @@ -159,8 +159,6 @@ int main(int argc, char* argv[]) { bool is_store = (is_mem_access && pick_one(3,minor_op)); bool is_conditional = (is_cflow || is_imm_cbranch) && !(is(0xE, minor_op) || is(0xF, minor_op)); - // TODO 2021: Add additional control signals you may need below.... - // setting up operand fetch and register read and write for the datapath: bool use_imm = is_imm_movq | is_imm_arithmetic | is_imm_cbranch; val reg_read_dz = or(use_if(!is_leaq, reg_d), use_if(is_leaq, reg_z)); @@ -231,7 +229,7 @@ int main(int argc, char* argv[]) { // determine the next position of the program counter bool is_jump = is_cflow && (is(0xF,minor_op) || (is_conditional && !reduce_or(compute_result))); - val pc_next_if_not_control = use_if(!is_jump, pc_incremented); + val pc_next_if_not_control = use_if(!(is_jump || is_return), pc_incremented); val pc_next_if_jump = use_if(is_jump, target); val pc_next_if_return = use_if(is_return, reg_out_b); val pc_next = add(add(pc_next_if_not_control, pc_next_if_jump), pc_next_if_return); @@ -242,7 +240,6 @@ int main(int argc, char* argv[]) { /*** WRITE ***/ // choose result to write back to register - // TODO 2021: Add any additional results which need to be muxed in for writing to the destination register bool use_compute_result = !is_load && (use_agen || use_multiplier || use_shifter || use_direct || use_alu); val datapath_result = or(use_if(use_compute_result, compute_result), use_if(is_load, mem_out)); @@ -251,7 +248,6 @@ int main(int argc, char* argv[]) { reg_write(regs, reg_d, datapath_result, reg_wr_enable); // write to memory if needed - printf("%i\n",is_store); memory_write(mem, agen_result, reg_out_a, is_store); // update program counter diff --git a/A5/sim b/A5/sim index de17651..3540256 100755 Binary files a/A5/sim and b/A5/sim differ diff --git a/A5/test_runs/test1.out b/A5/test_runs/test1.out index 359d574..77e32a5 100644 --- a/A5/test_runs/test1.out +++ b/A5/test_runs/test1.out @@ -1,25 +1,13 @@ 1 0 -0 2 6 -0 3 c -0 4 12 -0 5 15 -0 6 17 -0 7 1d -0 8 1f -0 9 22 -0 10 24 -0 11 2a -0 12 2c -0 Done diff --git a/A5/test_runs/test2.out b/A5/test_runs/test2.out index 9101694..7d92549 100644 --- a/A5/test_runs/test2.out +++ b/A5/test_runs/test2.out @@ -1,18 +1,9 @@ 1 0 -0 2 6 -1 3 8 -0 4 b -0 5 25 -0 6 3d -0 7 3f -0 8 45 -0 - -- value mismatch, access 'P' 0 - -- with value 47, but tracefile expected 0 +Done diff --git a/A5/test_runs/test3.hex b/A5/test_runs/test3.hex new file mode 100644 index 0000000..d7412c2 --- /dev/null +++ b/A5/test_runs/test3.hex @@ -0,0 +1,9 @@ +00000000 : # test: +00000000 : 645064000000 # movq $100, %rsi +00000006 : 64000a000000 # movq $10, %rax +0000000c : 3905 # movq %rax, (%rsi) +0000000e : 500002000000 # addq $2, %rax +00000014 : 3105 # movq (%rsi), %rax +00000016 : 500002000000 # addq $2, %rax +0000001c : 3905 # movq %rax, (%rsi) +0000001e : 0000 # stop diff --git a/A5/test_runs/test3.out b/A5/test_runs/test3.out new file mode 100644 index 0000000..e36cac6 --- /dev/null +++ b/A5/test_runs/test3.out @@ -0,0 +1,9 @@ +1 0 +2 6 +3 c +4 e +5 14 +6 16 +7 1c +8 1e +Done diff --git a/A5/test_runs/test3.sym b/A5/test_runs/test3.sym new file mode 100644 index 0000000..7791d92 --- /dev/null +++ b/A5/test_runs/test3.sym @@ -0,0 +1 @@ +test : 00000000 diff --git a/A5/test_runs/test3.trc b/A5/test_runs/test3.trc new file mode 100644 index 0000000..fbcae64 --- /dev/null +++ b/A5/test_runs/test3.trc @@ -0,0 +1,16 @@ +P 0 0 +R 5 64 +P 0 6 +R 0 a +P 0 c +M 64 a +P 0 e +R 0 c +P 0 14 +R 0 a +P 0 16 +R 0 c +P 0 1c +M 64 c +P 0 1e +P 0 20 diff --git a/A5/tests/test3.prime b/A5/tests/test3.prime new file mode 100644 index 0000000..9595567 --- /dev/null +++ b/A5/tests/test3.prime @@ -0,0 +1,9 @@ +test: + movq $100, %rsi + movq $10, %rax + movq %rax, (%rsi) + addq $2, %rax + movq (%rsi), %rax + addq $2, %rax + movq %rax, (%rsi) +stop \ No newline at end of file